50 lines
2.0 KiB
Diff
50 lines
2.0 KiB
Diff
From 10ac121c7e63d7abb856ec795b124dedf8dd9f49 Mon Sep 17 00:00:00 2001
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From: Martino Facchin <m.facchin@arduino.cc>
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Date: Thu, 2 Nov 2023 13:49:35 +0100
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Subject: [PATCH] stm32h7: adc: use CLKP as clock source
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Fixes analogRead() interferring with DSI/SDRAM
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---
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.../TARGET_STM32H7/analogin_device.c | 25 +------------------
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1 file changed, 1 insertion(+), 24 deletions(-)
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diff --git a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c
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index be16b16cda..8b617e307a 100644
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--- a/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c
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+++ b/targets/TARGET_STM/TARGET_STM32H7/analogin_device.c
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@@ -36,30 +36,7 @@ void analogin_pll_configuration(void)
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADC;
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- if(__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI) {
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- PeriphClkInitStruct.PLL2.PLL2M = 16;
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- PeriphClkInitStruct.PLL2.PLL2N = 120;
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- } else {
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- #if HSE_VALUE==8000000
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- PeriphClkInitStruct.PLL2.PLL2M = 2;
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- PeriphClkInitStruct.PLL2.PLL2N = 120;
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- #elif HSE_VALUE==16000000
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- PeriphClkInitStruct.PLL2.PLL2M = 2;
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- PeriphClkInitStruct.PLL2.PLL2N = 60;
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- #elif HSE_VALUE==25000000
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- PeriphClkInitStruct.PLL2.PLL2M = 5;
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- PeriphClkInitStruct.PLL2.PLL2N = 96;
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- #else
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- error("HSE not configured properly");
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- #endif
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- }
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- PeriphClkInitStruct.PLL2.PLL2P = 3;
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- PeriphClkInitStruct.PLL2.PLL2Q = 4;
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- PeriphClkInitStruct.PLL2.PLL2R = 2;
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- PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_1;
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- PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE;
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- PeriphClkInitStruct.PLL2.PLL2FRACN = 0;
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- PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;
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+ PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_CLKP;
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if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
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error("analogin_init HAL_RCCEx_PeriphCLKConfig");
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}
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--
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2.42.0
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