114 lines
4.3 KiB
Diff
114 lines
4.3 KiB
Diff
From b5881034882289d9221d628a748dfea73aa6cc7f Mon Sep 17 00:00:00 2001
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From: Martino Facchin <m.facchin@arduino.cc>
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Date: Fri, 17 Feb 2023 16:40:01 +0100
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Subject: [PATCH 201/204] whd: portentah7: fix dcache maintenance
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---
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.../COMPONENT_WHD/port/cyhal_sdio.c | 55 +++++++++++++------
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1 file changed, 39 insertions(+), 16 deletions(-)
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diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_sdio.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_sdio.c
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index 34aa5498e1..3ddfd85848 100644
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--- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_sdio.c
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+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/COMPONENT_WHD/port/cyhal_sdio.c
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@@ -63,6 +63,27 @@
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#define LINK_MTU 1024
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#define MAX(a,b) (a>b)?a:b
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+/* D-cache maintenance for DMA buffers */
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+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
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+ #define _CYHAL_DCACHE_MAINTENANCE
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+ #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (32u)
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+#else
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+ #define _CYHAL_DMA_BUFFER_ALIGN_BYTES (4u)
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+#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */
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+
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+/* Macro to ALIGN */
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+#if defined (__ARMCC_VERSION) /* ARM Compiler */
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+ #define ALIGN_HAL_COMMON(buf, x) __align(x) buf
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+#elif defined (__GNUC__) /* GNU Compiler */
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+ #define ALIGN_HAL_COMMON(buf, x) buf __attribute__ ((aligned (x)))
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+#elif defined (__ICCARM__) /* IAR Compiler */
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+ #define ALIGN_HAL_COMMON(buf, x) __ALIGNED(x) buf
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+#endif
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+
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+/* Macro to get variable aligned for cache maintenance purpose */
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+#define CYHAL_ALIGN_DMA_BUFFER(arg) ALIGN_HAL_COMMON(arg, _CYHAL_DMA_BUFFER_ALIGN_BYTES)
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+
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+
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extern pinconfig_t PinConfig[];
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extern SD_HandleTypeDef hsd;
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@@ -74,7 +95,7 @@ static uint32_t dctrl;
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static whd_driver_t whd_handler;
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static cyhal_sdio_irq_handler_t sdio_irq_handler;
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-static uint8_t temp_dma_buffer[2048] __attribute__((aligned(8)));
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+CYHAL_ALIGN_DMA_BUFFER(static uint8_t temp_dma_buffer[2048]);
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static uint8_t *user_data;
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static uint32_t user_data_size;
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static uint8_t *dma_data_source;
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@@ -150,22 +171,24 @@ static void sdio_prepare_data_transfer(cyhal_transfer_t direction, uint32_t bloc
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dma_transfer_size = (uint32_t)(((data_size + (uint16_t) block_size - 1) / (uint16_t) block_size) * (uint16_t) block_size);
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if (direction == CYHAL_WRITE) {
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-
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-#if !(defined(DUAL_CORE) && defined(CORE_CM4))
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- SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32);
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-#endif
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memcpy(temp_dma_buffer, data, data_size);
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dma_data_source = temp_dma_buffer;
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} else {
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dma_data_source = (uint8_t *)temp_dma_buffer;
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- //VIKR
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- //memset(dma_data_source,0x12,data_size);
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+ }
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-#if !(defined(DUAL_CORE) && defined(CORE_CM4))
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+#ifdef _CYHAL_DCACHE_MAINTENANCE
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+ if (direction == CYHAL_WRITE)
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+ {
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+ SCB_CleanDCache_by_Addr((uint32_t*)dma_data_source, block_size * dma_transfer_size);
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+ }
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+ else
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+ {
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/* Cache-Invalidate the output from DMA */
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- SCB_CleanDCache_by_Addr((uint32_t *)dma_data_source, data_size + 32);
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-#endif
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+ SCB_InvalidateDCache_by_Addr((uint32_t*)dma_data_source,
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+ data_size + __SCB_DCACHE_LINE_SIZE);
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}
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+#endif
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SDIO->DTIMER = (uint32_t) 0xFFFFFFFF;
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SDIO->DLEN = dma_transfer_size;
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@@ -252,12 +275,6 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk,
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/* Enable the SDIO Clock */
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__HAL_RCC_SDMMC1_CLK_ENABLE();
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-#if !(defined(DUAL_CORE) && defined(CORE_CM4))
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- /* Disable DCache for STM32H7 family */
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- SCB_CleanDCache();
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- SCB_DisableDCache();
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-#endif
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-
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WPRINT_WHD_DEBUG(("in init: %p\n", sdio_transfer_finished_semaphore));
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// Lower speed configuration
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@@ -437,6 +454,12 @@ restart:
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}
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if (direction == CYHAL_READ) {
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+ #ifdef _CYHAL_DCACHE_MAINTENANCE
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+ SCB_CleanInvalidateDCache_by_Addr(
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+ (uint32_t*)((uint32_t)dma_data_source & ~(__SCB_DCACHE_LINE_SIZE - 1U)),
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+ user_data_size + __SCB_DCACHE_LINE_SIZE);
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+ #endif /* if defined(_CYHAL_DCACHE_MAINTENANCE) */
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+
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memcpy(user_data, dma_data_source, (size_t) user_data_size);
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}
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--
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2.39.1
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