read dipswitch function

This commit is contained in:
Martijn Scheepers
2022-05-06 09:17:31 +02:00
parent 73735ff145
commit 3d7407368d
4 changed files with 29 additions and 13 deletions

View File

@@ -19,8 +19,6 @@ static QueueHandle_t H2201_encoder_volume_queue = NULL;
static uint32_t encoder_pcnt_unit = 0; static uint32_t encoder_pcnt_unit = 0;
void H2201_shiftregister_read(void);
static void IRAM_ATTR gpio_isr_handler(void *arg) static void IRAM_ATTR gpio_isr_handler(void *arg)
{ {
uint32_t gpio_num = (uint32_t)arg; uint32_t gpio_num = (uint32_t)arg;
@@ -54,7 +52,15 @@ static void H2201_button_task(void *arg)
H2201_i2c_mastervolume_down(); H2201_i2c_mastervolume_down();
} }
} }
H2201_shiftregister_read();
// printf("1=%d ", H2201_dipswitch_read(1));
// printf("2=%d ", H2201_dipswitch_read(2));
// printf("3=%d ", H2201_dipswitch_read(3));
// printf("4=%d ", H2201_dipswitch_read(4));
// printf("5=%d ", H2201_dipswitch_read(5));
// printf("6=%d ", H2201_dipswitch_read(6));
// printf("7=%d ", H2201_dipswitch_read(7));
// printf("8=%d\n", H2201_dipswitch_read(8));
} }
} }
//******************* shiftregsiter ******************************** //******************* shiftregsiter ********************************
@@ -65,23 +71,32 @@ void H2201_shiftregister_init(void)
gpio_set_direction(SHIFT_DATA, GPIO_MODE_INPUT); gpio_set_direction(SHIFT_DATA, GPIO_MODE_INPUT);
} }
void H2201_shiftregister_read() void H2201_shiftregister_read(bool dipswitch[9])
{ {
bool dipswitch[9]; // clock inputs in registers
gpio_set_level(SHIFT_LATCH, 1); gpio_set_level(SHIFT_LATCH, 1);
gpio_set_level(SHIFT_CLOCK, 1); gpio_set_level(SHIFT_CLOCK, 1);
gpio_set_level(SHIFT_CLOCK, 0); gpio_set_level(SHIFT_CLOCK, 0);
gpio_set_level(SHIFT_LATCH, 0); gpio_set_level(SHIFT_LATCH, 0);
// get de bits
for (size_t i = 8; i > 0; --i) for (size_t i = 8; i > 0; --i)
{ {
gpio_set_level(SHIFT_CLOCK, 1); gpio_set_level(SHIFT_CLOCK, 1);
dipswitch[i] = gpio_get_level(SHIFT_DATA); dipswitch[i] = gpio_get_level(SHIFT_DATA);
gpio_set_level(SHIFT_CLOCK, 0); gpio_set_level(SHIFT_CLOCK, 0);
} }
}
printf("1=%d 2=%d 3=%d 4=%d 5=%d 6=%d 7=%d 8=%d\n", dipswitch[1], dipswitch[2], dipswitch[3], dipswitch[4], dipswitch[5], dipswitch[6], dipswitch[7], dipswitch[8]); bool H2201_dipswitch_read(int sw)
{
if (sw < 0 || sw > 8)
{
return false;
}
bool dipswitch[9];
H2201_shiftregister_read(dipswitch);
return dipswitch[sw];
} }
//******************* buttons ******************************** //******************* buttons ********************************

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@@ -24,6 +24,7 @@ typedef struct {
} pcnt_evt_t; } pcnt_evt_t;
void H2201_shiftregister_init(void); void H2201_shiftregister_init(void);
bool H2201_dipswitch_read(int sw);
void H2201_buttons_init(void); void H2201_buttons_init(void);
void H2201_encoder_init(void); void H2201_encoder_init(void);

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@@ -184,7 +184,7 @@ CONFIG_BT_ENABLED=y
# CONFIG_BTDM_CTRL_MODE_BLE_ONLY is not set # CONFIG_BTDM_CTRL_MODE_BLE_ONLY is not set
CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y
# CONFIG_BTDM_CTRL_MODE_BTDM is not set # CONFIG_BTDM_CTRL_MODE_BTDM is not set
CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN=2 CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN=1
CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN=0 CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN=0
# CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_HCI is not set # CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_HCI is not set
CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_PCM=y CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_PCM=y
@@ -199,7 +199,7 @@ CONFIG_BTDM_CTRL_PCM_POLAR_EFF=0
CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT=y CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT=y
CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF=y CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF=y
CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0 CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0
CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=2 CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=1
CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0 CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0
CONFIG_BTDM_CTRL_PINNED_TO_CORE_0=y CONFIG_BTDM_CTRL_PINNED_TO_CORE_0=y
# CONFIG_BTDM_CTRL_PINNED_TO_CORE_1 is not set # CONFIG_BTDM_CTRL_PINNED_TO_CORE_1 is not set
@@ -1521,10 +1521,10 @@ CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
# CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY is not set # CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY is not set
CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY=y CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY=y
# CONFIG_BTDM_CONTROLLER_MODE_BTDM is not set # CONFIG_BTDM_CONTROLLER_MODE_BTDM is not set
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN=2 CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN=1
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN=0 CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN=0
CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0 CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=2 CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=1
CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0 CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0
CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0 CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0
CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI=y CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI=y

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@@ -783,7 +783,7 @@ CONFIG_ESP_TIMER_IMPL_TG0_LAC=y
# Wi-Fi # Wi-Fi
# #
CONFIG_ESP32_WIFI_ENABLED=y CONFIG_ESP32_WIFI_ENABLED=y
CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE=y # CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE is not set
CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10 CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32 CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set # CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
@@ -1763,7 +1763,7 @@ CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set # CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
CONFIG_TIMER_TASK_STACK_SIZE=3584 CONFIG_TIMER_TASK_STACK_SIZE=3584
CONFIG_SW_COEXIST_ENABLE=y # CONFIG_SW_COEXIST_ENABLE is not set
# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set # CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set # CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y