read dipswitch function
This commit is contained in:
@@ -19,8 +19,6 @@ static QueueHandle_t H2201_encoder_volume_queue = NULL;
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static uint32_t encoder_pcnt_unit = 0;
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static uint32_t encoder_pcnt_unit = 0;
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void H2201_shiftregister_read(void);
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static void IRAM_ATTR gpio_isr_handler(void *arg)
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static void IRAM_ATTR gpio_isr_handler(void *arg)
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{
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{
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uint32_t gpio_num = (uint32_t)arg;
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uint32_t gpio_num = (uint32_t)arg;
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@@ -54,7 +52,15 @@ static void H2201_button_task(void *arg)
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H2201_i2c_mastervolume_down();
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H2201_i2c_mastervolume_down();
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}
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}
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}
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}
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H2201_shiftregister_read();
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// printf("1=%d ", H2201_dipswitch_read(1));
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// printf("2=%d ", H2201_dipswitch_read(2));
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// printf("3=%d ", H2201_dipswitch_read(3));
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// printf("4=%d ", H2201_dipswitch_read(4));
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// printf("5=%d ", H2201_dipswitch_read(5));
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// printf("6=%d ", H2201_dipswitch_read(6));
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// printf("7=%d ", H2201_dipswitch_read(7));
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// printf("8=%d\n", H2201_dipswitch_read(8));
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}
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}
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}
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}
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//******************* shiftregsiter ********************************
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//******************* shiftregsiter ********************************
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@@ -65,23 +71,32 @@ void H2201_shiftregister_init(void)
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gpio_set_direction(SHIFT_DATA, GPIO_MODE_INPUT);
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gpio_set_direction(SHIFT_DATA, GPIO_MODE_INPUT);
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}
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}
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void H2201_shiftregister_read()
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void H2201_shiftregister_read(bool dipswitch[9])
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{
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{
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bool dipswitch[9];
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// clock inputs in registers
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gpio_set_level(SHIFT_LATCH, 1);
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gpio_set_level(SHIFT_LATCH, 1);
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gpio_set_level(SHIFT_CLOCK, 1);
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gpio_set_level(SHIFT_CLOCK, 1);
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gpio_set_level(SHIFT_CLOCK, 0);
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gpio_set_level(SHIFT_CLOCK, 0);
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gpio_set_level(SHIFT_LATCH, 0);
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gpio_set_level(SHIFT_LATCH, 0);
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// get de bits
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for (size_t i = 8; i > 0; --i)
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for (size_t i = 8; i > 0; --i)
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{
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{
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gpio_set_level(SHIFT_CLOCK, 1);
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gpio_set_level(SHIFT_CLOCK, 1);
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dipswitch[i] = gpio_get_level(SHIFT_DATA);
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dipswitch[i] = gpio_get_level(SHIFT_DATA);
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gpio_set_level(SHIFT_CLOCK, 0);
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gpio_set_level(SHIFT_CLOCK, 0);
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}
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}
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}
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printf("1=%d 2=%d 3=%d 4=%d 5=%d 6=%d 7=%d 8=%d\n", dipswitch[1], dipswitch[2], dipswitch[3], dipswitch[4], dipswitch[5], dipswitch[6], dipswitch[7], dipswitch[8]);
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bool H2201_dipswitch_read(int sw)
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{
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if (sw < 0 || sw > 8)
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{
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return false;
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}
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bool dipswitch[9];
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H2201_shiftregister_read(dipswitch);
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return dipswitch[sw];
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}
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}
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//******************* buttons ********************************
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//******************* buttons ********************************
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@@ -24,6 +24,7 @@ typedef struct {
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} pcnt_evt_t;
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} pcnt_evt_t;
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void H2201_shiftregister_init(void);
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void H2201_shiftregister_init(void);
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bool H2201_dipswitch_read(int sw);
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void H2201_buttons_init(void);
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void H2201_buttons_init(void);
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void H2201_encoder_init(void);
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void H2201_encoder_init(void);
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@@ -184,7 +184,7 @@ CONFIG_BT_ENABLED=y
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# CONFIG_BTDM_CTRL_MODE_BLE_ONLY is not set
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# CONFIG_BTDM_CTRL_MODE_BLE_ONLY is not set
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CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y
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CONFIG_BTDM_CTRL_MODE_BR_EDR_ONLY=y
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# CONFIG_BTDM_CTRL_MODE_BTDM is not set
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# CONFIG_BTDM_CTRL_MODE_BTDM is not set
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CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN=2
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CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN=1
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CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN=0
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CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN=0
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# CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_HCI is not set
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# CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_HCI is not set
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CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_PCM=y
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CONFIG_BTDM_CTRL_BR_EDR_SCO_DATA_PATH_PCM=y
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@@ -199,7 +199,7 @@ CONFIG_BTDM_CTRL_PCM_POLAR_EFF=0
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CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT=y
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CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT=y
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CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF=y
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CONFIG_BTDM_CTRL_LEGACY_AUTH_VENDOR_EVT_EFF=y
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CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0
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CONFIG_BTDM_CTRL_BLE_MAX_CONN_EFF=0
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CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=2
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CONFIG_BTDM_CTRL_BR_EDR_MAX_ACL_CONN_EFF=1
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CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0
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CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF=0
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CONFIG_BTDM_CTRL_PINNED_TO_CORE_0=y
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CONFIG_BTDM_CTRL_PINNED_TO_CORE_0=y
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# CONFIG_BTDM_CTRL_PINNED_TO_CORE_1 is not set
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# CONFIG_BTDM_CTRL_PINNED_TO_CORE_1 is not set
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@@ -1521,10 +1521,10 @@ CONFIG_ESP32_APPTRACE_LOCK_ENABLE=y
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# CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY is not set
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# CONFIG_BTDM_CONTROLLER_MODE_BLE_ONLY is not set
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CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY=y
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CONFIG_BTDM_CONTROLLER_MODE_BR_EDR_ONLY=y
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# CONFIG_BTDM_CONTROLLER_MODE_BTDM is not set
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# CONFIG_BTDM_CONTROLLER_MODE_BTDM is not set
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CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN=2
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CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN=1
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CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN=0
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CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN=0
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CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0
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CONFIG_BTDM_CONTROLLER_BLE_MAX_CONN_EFF=0
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CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=2
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CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_EFF=1
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CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0
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CONFIG_BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_EFF=0
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CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0
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CONFIG_BTDM_CONTROLLER_PINNED_TO_CORE=0
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CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI=y
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CONFIG_BTDM_CONTROLLER_HCI_MODE_VHCI=y
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@@ -783,7 +783,7 @@ CONFIG_ESP_TIMER_IMPL_TG0_LAC=y
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# Wi-Fi
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# Wi-Fi
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#
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#
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CONFIG_ESP32_WIFI_ENABLED=y
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CONFIG_ESP32_WIFI_ENABLED=y
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CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE=y
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# CONFIG_ESP32_WIFI_SW_COEXIST_ENABLE is not set
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CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
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CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM=10
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CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
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CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM=32
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# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
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# CONFIG_ESP32_WIFI_STATIC_TX_BUFFER is not set
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@@ -1763,7 +1763,7 @@ CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU0=y
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CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
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CONFIG_TASK_WDT_CHECK_IDLE_TASK_CPU1=y
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# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
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# CONFIG_ESP32_DEBUG_STUBS_ENABLE is not set
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CONFIG_TIMER_TASK_STACK_SIZE=3584
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CONFIG_TIMER_TASK_STACK_SIZE=3584
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CONFIG_SW_COEXIST_ENABLE=y
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# CONFIG_SW_COEXIST_ENABLE is not set
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# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
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# CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH is not set
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# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
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# CONFIG_ESP32_ENABLE_COREDUMP_TO_UART is not set
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CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
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CONFIG_ESP32_ENABLE_COREDUMP_TO_NONE=y
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