sigma studio output
This commit is contained in:
Martijn Scheepers
14
ADAU1761/IC 1_H2201_V1/ParamAddress.dat
Normal file
14
ADAU1761/IC 1_H2201_V1/ParamAddress.dat
Normal file
@@ -0,0 +1,14 @@
|
||||
NonModRamAlloc 0
|
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dataLoadStart_SafeLoad 1
|
||||
dataLoad1_SafeLoad 2
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dataLoad2_SafeLoad 3
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dataLoad3_SafeLoad 4
|
||||
dataLoadEnd_SafeLoad 5
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||||
addressLoad_SafeLoad 6
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||||
numLoad_SafeLoad 7
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NxNMixer1940Alg1_00_00_1 8
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NxNMixer1940Alg1_00_01_1 9
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NxNMixer1940Alg2_00_00_2 10
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NxNMixer1940Alg2_00_01_2 11
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Gain1940AlgNS1_3 12
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Gain1940AlgNS2_4 13
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40
ADAU1761/IC 1_H2201_V1/compiler_output.txt
Normal file
40
ADAU1761/IC 1_H2201_V1/compiler_output.txt
Normal file
@@ -0,0 +1,40 @@
|
||||
Sigma Studio Version 4.6. Build 0, Rev 1809
|
||||
|
||||
Analog Devices Compiler for the 3rd generation SigmaDSP core.
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Build date = 12/23/2020 at 4:27 AM
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||||
## Summary ##
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(Note: Estimates are based on a 48 kHz sample rate)
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Instructions used:
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63 (out of a possible 1024 )
|
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Modulo Data RAM used (X Memory):
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8 (out of a possible 4096 )
|
||||
Non Modulo Data RAM used (X Memory):
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0 (out of a possible 4096 )
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Parameter RAM used (Y Memory):
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14 (out of a possible 1024 )
|
||||
|
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Instance Mips Inst Data Coeff Other
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(max)
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Beginning 19 19 0 1
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SafeLoadCode 15 15 0 7
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Input1 8 8 4 0
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End 5 5 0 0
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NxM Mixer2 3 3 1 2
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NxM Mixer1 3 3 1 2
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Single 2 3 3 1 1
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Single 1 3 3 1 1
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Output1 2 2 0 0
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Output2 2 2 0 0
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Subroutines called:
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----------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Total 63 63 8 14
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----------------------------------------------------------------------------------------------------------------------------------------------------------------------
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||||
(%) 6% 6% 0% 1%
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|
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Files written:
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program_data.dat - load file for downloading code using ADI loader
|
||||
hex_program_data.dat - load file for downloading code using microcontroller
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ParamAddress.dat - Parameter RAM locations for schematic instances
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||||
63
ADAU1761/IC 1_H2201_V1/hex_program_data.dat
Normal file
63
ADAU1761/IC 1_H2201_V1/hex_program_data.dat
Normal file
@@ -0,0 +1,63 @@
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFE , 0xE0 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFF , 0x34 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFF , 0x2C , 0x00 , 0x00 , 0x00 ,
|
||||
0xFF , 0x54 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFF , 0x5C , 0x00 , 0x00 , 0x00 ,
|
||||
0xFF , 0xF5 , 0x08 , 0x20 , 0x00 ,
|
||||
0xFF , 0x38 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFF , 0x80 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFE , 0xE8 , 0x0C , 0x00 , 0x00 ,
|
||||
0xFE , 0x30 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFF , 0xE8 , 0x07 , 0x20 , 0x08 ,
|
||||
0x00 , 0x00 , 0x06 , 0xA0 , 0x00 ,
|
||||
0xFF , 0xE0 , 0x00 , 0xC0 , 0x00 ,
|
||||
0xFF , 0x80 , 0x07 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFF , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFE , 0xC0 , 0x22 , 0x00 , 0x27 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFE , 0xE8 , 0x1E , 0x00 , 0x00 ,
|
||||
0xFF , 0xE8 , 0x01 , 0x20 , 0x00 ,
|
||||
0xFF , 0xD8 , 0x01 , 0x03 , 0x00 ,
|
||||
0x00 , 0x07 , 0xC6 , 0x00 , 0x00 ,
|
||||
0xFF , 0x08 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFF , 0xF4 , 0x00 , 0x20 , 0x00 ,
|
||||
0xFF , 0xD8 , 0x07 , 0x02 , 0x00 ,
|
||||
0xFD , 0xA5 , 0x08 , 0x20 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0xE2 , 0x00 ,
|
||||
0xFD , 0xAD , 0x08 , 0x20 , 0x00 ,
|
||||
0x00 , 0x08 , 0x00 , 0xE2 , 0x00 ,
|
||||
0xFD , 0x25 , 0x08 , 0x20 , 0x00 ,
|
||||
0x00 , 0x10 , 0x00 , 0xE2 , 0x00 ,
|
||||
0xFD , 0x2D , 0x08 , 0x20 , 0x00 ,
|
||||
0x00 , 0x18 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x00 , 0x08 , 0x20 , 0x00 ,
|
||||
0x00 , 0x10 , 0x09 , 0x22 , 0x00 ,
|
||||
0x00 , 0x20 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x08 , 0x0A , 0x20 , 0x00 ,
|
||||
0x00 , 0x18 , 0x0B , 0x22 , 0x00 ,
|
||||
0x00 , 0x28 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x28 , 0x0C , 0x20 , 0x00 ,
|
||||
0x00 , 0x30 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x20 , 0x0D , 0x20 , 0x00 ,
|
||||
0x00 , 0x38 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x3D , 0x08 , 0x20 , 0x00 ,
|
||||
0xFD , 0xB0 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x35 , 0x08 , 0x20 , 0x00 ,
|
||||
0xFD , 0xB8 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFE , 0x30 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFE , 0xC0 , 0x0F , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
63
ADAU1761/IC 1_H2201_V1/hex_program_simdata.dat
Normal file
63
ADAU1761/IC 1_H2201_V1/hex_program_simdata.dat
Normal file
@@ -0,0 +1,63 @@
|
||||
0000000000
|
||||
FEE0000000
|
||||
FF34000000
|
||||
FF2C000000
|
||||
FF54000000
|
||||
FF5C000000
|
||||
FFF5082000
|
||||
FF38000000
|
||||
FF80000000
|
||||
0000000000
|
||||
0000000000
|
||||
FEE80C0000
|
||||
FE3000E200
|
||||
0000000000
|
||||
0000000000
|
||||
0000000000
|
||||
0000000000
|
||||
0000000000
|
||||
0000000000
|
||||
FFE8072008
|
||||
000006A000
|
||||
FFE000C000
|
||||
FF80070000
|
||||
0000000000
|
||||
FF00000000
|
||||
FEC0220027
|
||||
0000000000
|
||||
FEE81E0000
|
||||
FFE8012000
|
||||
FFD8010300
|
||||
0007C60000
|
||||
FF08000000
|
||||
FFF4002000
|
||||
FFD8070200
|
||||
FDA5082000
|
||||
000000E200
|
||||
FDAD082000
|
||||
000800E200
|
||||
FD25082000
|
||||
001000E200
|
||||
FD2D082000
|
||||
001800E200
|
||||
0000082000
|
||||
0010092200
|
||||
002000E200
|
||||
00080A2000
|
||||
00180B2200
|
||||
002800E200
|
||||
00280C2000
|
||||
003000E200
|
||||
0000000000
|
||||
00200D2000
|
||||
003800E200
|
||||
0000000000
|
||||
003D082000
|
||||
FDB000E200
|
||||
0035082000
|
||||
FDB800E200
|
||||
0000000000
|
||||
FE30000000
|
||||
0000000000
|
||||
FEC00F0000
|
||||
0000000000
|
||||
63
ADAU1761/IC 1_H2201_V1/program_data.dat
Normal file
63
ADAU1761/IC 1_H2201_V1/program_data.dat
Normal file
@@ -0,0 +1,63 @@
|
||||
0000000000000000000000000000000000000000
|
||||
1111111011100000000000000000000000000000
|
||||
1111111100110100000000000000000000000000
|
||||
1111111100101100000000000000000000000000
|
||||
1111111101010100000000000000000000000000
|
||||
1111111101011100000000000000000000000000
|
||||
1111111111110101000010000010000000000000
|
||||
1111111100111000000000000000000000000000
|
||||
1111111110000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
1111111011101000000011000000000000000000
|
||||
1111111000110000000000001110001000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
1111111111101000000001110010000000001000
|
||||
0000000000000000000001101010000000000000
|
||||
1111111111100000000000001100000000000000
|
||||
1111111110000000000001110000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
1111111100000000000000000000000000000000
|
||||
1111111011000000001000100000000000100111
|
||||
0000000000000000000000000000000000000000
|
||||
1111111011101000000111100000000000000000
|
||||
1111111111101000000000010010000000000000
|
||||
1111111111011000000000010000001100000000
|
||||
0000000000000111110001100000000000000000
|
||||
1111111100001000000000000000000000000000
|
||||
1111111111110100000000000010000000000000
|
||||
1111111111011000000001110000001000000000
|
||||
1111110110100101000010000010000000000000
|
||||
0000000000000000000000001110001000000000
|
||||
1111110110101101000010000010000000000000
|
||||
0000000000001000000000001110001000000000
|
||||
1111110100100101000010000010000000000000
|
||||
0000000000010000000000001110001000000000
|
||||
1111110100101101000010000010000000000000
|
||||
0000000000011000000000001110001000000000
|
||||
0000000000000000000010000010000000000000
|
||||
0000000000010000000010010010001000000000
|
||||
0000000000100000000000001110001000000000
|
||||
0000000000001000000010100010000000000000
|
||||
0000000000011000000010110010001000000000
|
||||
0000000000101000000000001110001000000000
|
||||
0000000000101000000011000010000000000000
|
||||
0000000000110000000000001110001000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000100000000011010010000000000000
|
||||
0000000000111000000000001110001000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000111101000010000010000000000000
|
||||
1111110110110000000000001110001000000000
|
||||
0000000000110101000010000010000000000000
|
||||
1111110110111000000000001110001000000000
|
||||
0000000000000000000000000000000000000000
|
||||
1111111000110000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
1111111011000000000011110000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
1
ADAU1761/IC 1_H2201_V1/report.dat
Normal file
1
ADAU1761/IC 1_H2201_V1/report.dat
Normal file
@@ -0,0 +1 @@
|
||||
OPCODE_COUNT,Program_Count,62
|
||||
15
ADAU1761/System/H2201_V1.hex
Normal file
15
ADAU1761/System/H2201_V1.hex
Normal file
@@ -0,0 +1,15 @@
|
||||
0x00 , 0x00 , 0x10 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
|
||||
96
ADAU1761/System/H2201_V1.params
Normal file
96
ADAU1761/System/H2201_V1.params
Normal file
@@ -0,0 +1,96 @@
|
||||
Cell Name = Single 1
|
||||
Parameter Name = Gain1940AlgNS1
|
||||
Parameter Address = 12
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
|
||||
|
||||
|
||||
Cell Name = Single 2
|
||||
Parameter Name = Gain1940AlgNS2
|
||||
Parameter Address = 13
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
|
||||
|
||||
|
||||
Cell Name = NxM Mixer1
|
||||
Parameter Name = NxNMixer1940Alg1_00_00
|
||||
Parameter Address = 8
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
|
||||
|
||||
|
||||
Cell Name = NxM Mixer1
|
||||
Parameter Name = NxNMixer1940Alg1_00_01
|
||||
Parameter Address = 9
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
|
||||
|
||||
|
||||
Cell Name = NxM Mixer2
|
||||
Parameter Name = NxNMixer1940Alg2_00_00
|
||||
Parameter Address = 10
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
|
||||
|
||||
|
||||
Cell Name = NxM Mixer2
|
||||
Parameter Name = NxNMixer1940Alg2_00_01
|
||||
Parameter Address = 11
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
|
||||
|
||||
|
||||
Cell Name = None - Framework
|
||||
Parameter Name = NonModRamAlloc
|
||||
Parameter Address = 0
|
||||
Parameter Value = 4096
|
||||
Parameter Data :
|
||||
0x00, 0x00, 0x10, 0x00,
|
||||
|
||||
|
||||
|
||||
Parameter data for: IC 1 (Hexadecimal format starting at parameter address 0)
|
||||
See also H2201_V1.hex file
|
||||
0x00 , 0x00 , 0x10 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
|
||||
Parameter data for: IC 1 (Binary format starting at parameter address 0)
|
||||
00000000 00000000 00010000 00000000
|
||||
00000000 00000000 00000000 00000000
|
||||
00000000 00000000 00000000 00000000
|
||||
00000000 00000000 00000000 00000000
|
||||
00000000 00000000 00000000 00000000
|
||||
00000000 00000000 00000000 00000000
|
||||
00000000 00000000 00000000 00000000
|
||||
00000000 00000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
|
||||
382
ADAU1761/System/H2201_V1.xml
Normal file
382
ADAU1761/System/H2201_V1.xml
Normal file
File diff suppressed because one or more lines are too long
340
ADAU1761/System/H2201_V1_IC_1.h
Normal file
340
ADAU1761/System/H2201_V1_IC_1.h
Normal file
@@ -0,0 +1,340 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC_1.h
|
||||
*
|
||||
* Created: Monday, April 25, 2022 11:45:56 AM
|
||||
* Description: H2201_V1:IC 1 program data.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __H2201_V1_IC_1_H__
|
||||
#define __H2201_V1_IC_1_H__
|
||||
|
||||
#include "SigmaStudioFW.h"
|
||||
#include "H2201_V1_IC_1_REG.h"
|
||||
|
||||
#define DEVICE_ARCHITECTURE_IC_1 "ADAU176x"
|
||||
#define DEVICE_ADDR_IC_1 0x70
|
||||
|
||||
/* DSP Program Data */
|
||||
#define PROGRAM_SIZE_IC_1 315
|
||||
#define PROGRAM_ADDR_IC_1 2048
|
||||
ADI_REG_TYPE Program_Data_IC_1[PROGRAM_SIZE_IC_1] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE0, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x34, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x2C, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x54, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x5C, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0xFF, 0x38, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x80, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE8, 0x0C, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x07, 0x20, 0x08,
|
||||
0x00, 0x00, 0x06, 0xA0, 0x00,
|
||||
0xFF, 0xE0, 0x00, 0xC0, 0x00,
|
||||
0xFF, 0x80, 0x07, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xC0, 0x22, 0x00, 0x27,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE8, 0x1E, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x01, 0x20, 0x00,
|
||||
0xFF, 0xD8, 0x01, 0x03, 0x00,
|
||||
0x00, 0x07, 0xC6, 0x00, 0x00,
|
||||
0xFF, 0x08, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xF4, 0x00, 0x20, 0x00,
|
||||
0xFF, 0xD8, 0x07, 0x02, 0x00,
|
||||
0xFD, 0xA5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x00, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0xAD, 0x08, 0x20, 0x00,
|
||||
0x00, 0x08, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x25, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x2D, 0x08, 0x20, 0x00,
|
||||
0x00, 0x18, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x09, 0x22, 0x00,
|
||||
0x00, 0x20, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x08, 0x0A, 0x20, 0x00,
|
||||
0x00, 0x18, 0x0B, 0x22, 0x00,
|
||||
0x00, 0x28, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x0C, 0x20, 0x00,
|
||||
0x00, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x20, 0x0D, 0x20, 0x00,
|
||||
0x00, 0x38, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x35, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xC0, 0x0F, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
};
|
||||
|
||||
/* DSP Parameter (Coefficient) Data */
|
||||
#define PARAM_SIZE_IC_1 56
|
||||
#define PARAM_ADDR_IC_1 0
|
||||
ADI_REG_TYPE Param_Data_IC_1[PARAM_SIZE_IC_1] = {
|
||||
0x00, 0x00, 0x10, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00, 0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00,
|
||||
0x80, 0x00, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00,
|
||||
};
|
||||
|
||||
|
||||
/* Register Default - IC 1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R0_SAMPLE_RATE_SETTING_IC_1_Default[REG_SAMPLE_RATE_SETTING_IC_1_BYTE] = {
|
||||
0x7F
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.DSP Run Register */
|
||||
ADI_REG_TYPE R1_DSP_RUN_REGISTER_IC_1_Default[REG_DSP_RUN_REGISTER_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Clock Control Register */
|
||||
ADI_REG_TYPE R2_CLKCTRLREGISTER_IC_1_Default[REG_CLKCTRLREGISTER_IC_1_BYTE] = {
|
||||
0x0F
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.PLL Control Register */
|
||||
ADI_REG_TYPE R3_PLLCRLREGISTER_IC_1_Default[REG_PLLCRLREGISTER_IC_1_BYTE] = {
|
||||
0x00, 0x01, 0x00, 0x00, 0x20, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Delay */
|
||||
#define R4_DELAY_IC_1_ADDR 0x0
|
||||
#define R4_DELAY_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R4_DELAY_IC_1_Default[R4_DELAY_IC_1_SIZE] = {
|
||||
0x00, 0x64
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Serial Port Control Registers */
|
||||
#define R5_SERIAL_PORT_CONTROL_REGISTERS_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R5_SERIAL_PORT_CONTROL_REGISTERS_IC_1_Default[R5_SERIAL_PORT_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.ALC Control Registers */
|
||||
#define R6_ALC_CONTROL_REGISTERS_IC_1_SIZE 4
|
||||
ADI_REG_TYPE R6_ALC_CONTROL_REGISTERS_IC_1_Default[R6_ALC_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Microphone Control Register */
|
||||
ADI_REG_TYPE R7_MICCTRLREGISTER_IC_1_Default[REG_MICCTRLREGISTER_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Record Input Signal Path Registers */
|
||||
#define R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE 8
|
||||
ADI_REG_TYPE R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC_1_Default[R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE] = {
|
||||
0x00, 0x01, 0x05, 0x01, 0x05, 0x00, 0x00, 0x08
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.ADC Control Registers */
|
||||
#define R9_ADC_CONTROL_REGISTERS_IC_1_SIZE 3
|
||||
ADI_REG_TYPE R9_ADC_CONTROL_REGISTERS_IC_1_Default[R9_ADC_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0x13, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Playback Output Signal Path Registers */
|
||||
#define R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE 14
|
||||
ADI_REG_TYPE R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC_1_Default[R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE] = {
|
||||
0x61, 0x00, 0x61, 0x00, 0x0A, 0x0A, 0x00, 0xE7, 0xE7, 0x02, 0x02, 0xE7, 0x00, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Converter Control Registers */
|
||||
#define R11_CONVERTER_CONTROL_REGISTERS_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R11_CONVERTER_CONTROL_REGISTERS_IC_1_Default[R11_CONVERTER_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.DAC Control Registers */
|
||||
#define R12_DAC_CONTROL_REGISTERS_IC_1_SIZE 3
|
||||
ADI_REG_TYPE R12_DAC_CONTROL_REGISTERS_IC_1_Default[R12_DAC_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0x03, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Serial Port Pad Control Registers */
|
||||
#define R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE 1
|
||||
ADI_REG_TYPE R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC_1_Default[R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0xAA
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Communication Port Pad Control Registers */
|
||||
#define R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC_1_Default[R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0xAA, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Jack Detect Pad Control Register */
|
||||
ADI_REG_TYPE R15_JACKREGISTER_IC_1_Default[REG_JACKREGISTER_IC_1_BYTE] = {
|
||||
0x08
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.DSP ON Register */
|
||||
ADI_REG_TYPE R21_DSP_ENABLE_REGISTER_IC_1_Default[REG_DSP_ENABLE_REGISTER_IC_1_BYTE] = {
|
||||
0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.CRC Registers */
|
||||
#define R22_CRC_REGISTERS_IC_1_SIZE 5
|
||||
ADI_REG_TYPE R22_CRC_REGISTERS_IC_1_Default[R22_CRC_REGISTERS_IC_1_SIZE] = {
|
||||
0x7F, 0x7F, 0x60, 0x7F, 0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.GPIO Registers */
|
||||
#define R23_GPIO_REGISTERS_IC_1_SIZE 4
|
||||
ADI_REG_TYPE R23_GPIO_REGISTERS_IC_1_Default[R23_GPIO_REGISTERS_IC_1_SIZE] = {
|
||||
0x07, 0x07, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Non Modulo Registers */
|
||||
#define R24_NON_MODULO_REGISTERS_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R24_NON_MODULO_REGISTERS_IC_1_Default[R24_NON_MODULO_REGISTERS_IC_1_SIZE] = {
|
||||
0x10, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Watchdog Registers */
|
||||
#define R25_WATCHDOG_REGISTERS_IC_1_SIZE 5
|
||||
ADI_REG_TYPE R25_WATCHDOG_REGISTERS_IC_1_Default[R25_WATCHDOG_REGISTERS_IC_1_SIZE] = {
|
||||
0x00, 0x02, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Sampling Rate Setting Register */
|
||||
ADI_REG_TYPE R26_SAMPLE_RATE_SETTING_IC_1_Default[REG_SAMPLE_RATE_SETTING_IC_1_BYTE] = {
|
||||
0x7F
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Routing Matrix Inputs Register */
|
||||
ADI_REG_TYPE R27_ROUTING_MATRIX_INPUTS_IC_1_Default[REG_ROUTING_MATRIX_INPUTS_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Routing Matrix Outputs Register */
|
||||
ADI_REG_TYPE R28_ROUTING_MATRIX_OUTPUTS_IC_1_Default[REG_ROUTING_MATRIX_OUTPUTS_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Serial Data Configuration Register */
|
||||
ADI_REG_TYPE R29_SERIAL_DATAGPIO_PIN_CONFIG_IC_1_Default[REG_SERIAL_DATAGPIO_PIN_CONFIG_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.DSP Slew Mode Register */
|
||||
ADI_REG_TYPE R30_DSP_SLEW_MODES_IC_1_Default[REG_DSP_SLEW_MODES_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Serial Port Sample Rate Register */
|
||||
ADI_REG_TYPE R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC_1_Default[REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Clock Enable Registers */
|
||||
#define R32_CLOCK_ENABLE_REGISTERS_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R32_CLOCK_ENABLE_REGISTERS_IC_1_Default[R32_CLOCK_ENABLE_REGISTERS_IC_1_SIZE] = {
|
||||
0x7F, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R35_SAMPLE_RATE_SETTING_IC_1_Default[REG_SAMPLE_RATE_SETTING_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.DSP Run Register */
|
||||
ADI_REG_TYPE R36_DSP_RUN_REGISTER_IC_1_Default[REG_DSP_RUN_REGISTER_IC_1_BYTE] = {
|
||||
0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R37_DEJITTER_REGISTER_CONTROL_IC_1_Default[REG_DEJITTER_REGISTER_CONTROL_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R38_DEJITTER_REGISTER_CONTROL_IC_1_Default[REG_DEJITTER_REGISTER_CONTROL_IC_1_BYTE] = {
|
||||
0x03
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Default Download
|
||||
*/
|
||||
#define DEFAULT_DOWNLOAD_SIZE_IC_1 39
|
||||
|
||||
void default_download_IC_1() {
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SAMPLE_RATE_SETTING_IC_1_ADDR, REG_SAMPLE_RATE_SETTING_IC_1_BYTE, R0_SAMPLE_RATE_SETTING_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DSP_RUN_REGISTER_IC_1_ADDR, REG_DSP_RUN_REGISTER_IC_1_BYTE, R1_DSP_RUN_REGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_CLKCTRLREGISTER_IC_1_ADDR, REG_CLKCTRLREGISTER_IC_1_BYTE, R2_CLKCTRLREGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_PLLCRLREGISTER_IC_1_ADDR, REG_PLLCRLREGISTER_IC_1_BYTE, R3_PLLCRLREGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_DELAY( DEVICE_ADDR_IC_1, R4_DELAY_IC_1_SIZE, R4_DELAY_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SERIAL_PORT_CONTROL_0_IC_1_ADDR , R5_SERIAL_PORT_CONTROL_REGISTERS_IC_1_SIZE, R5_SERIAL_PORT_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_ALC_CONTROL_0_IC_1_ADDR , R6_ALC_CONTROL_REGISTERS_IC_1_SIZE, R6_ALC_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_MICCTRLREGISTER_IC_1_ADDR, REG_MICCTRLREGISTER_IC_1_BYTE, R7_MICCTRLREGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_RECORD_PWR_MANAGEMENT_IC_1_ADDR , R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE, R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_ADC_CONTROL_0_IC_1_ADDR , R9_ADC_CONTROL_REGISTERS_IC_1_SIZE, R9_ADC_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_PLAYBACK_MIXER_LEFT_CONTROL_0_IC_1_ADDR , R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE, R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_CONVERTER_CTRL_0_IC_1_ADDR , R11_CONVERTER_CONTROL_REGISTERS_IC_1_SIZE, R11_CONVERTER_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DAC_CONTROL_0_IC_1_ADDR , R12_DAC_CONTROL_REGISTERS_IC_1_SIZE, R12_DAC_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SERIAL_PORT_PAD_CONTROL_0_IC_1_ADDR , R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE, R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_COMM_PORT_PAD_CTRL_0_IC_1_ADDR , R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE, R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_JACKREGISTER_IC_1_ADDR, REG_JACKREGISTER_IC_1_BYTE, R15_JACKREGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DSP_ENABLE_REGISTER_IC_1_ADDR, REG_DSP_ENABLE_REGISTER_IC_1_BYTE, R21_DSP_ENABLE_REGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_CRC_IDEAL_1_IC_1_ADDR , R22_CRC_REGISTERS_IC_1_SIZE, R22_CRC_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_GPIO_0_CONTROL_IC_1_ADDR , R23_GPIO_REGISTERS_IC_1_SIZE, R23_GPIO_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_NON_MODULO_RAM_1_IC_1_ADDR , R24_NON_MODULO_REGISTERS_IC_1_SIZE, R24_NON_MODULO_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_WATCHDOG_ENABLE_IC_1_ADDR , R25_WATCHDOG_REGISTERS_IC_1_SIZE, R25_WATCHDOG_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SAMPLE_RATE_SETTING_IC_1_ADDR, REG_SAMPLE_RATE_SETTING_IC_1_BYTE, R26_SAMPLE_RATE_SETTING_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_ROUTING_MATRIX_INPUTS_IC_1_ADDR, REG_ROUTING_MATRIX_INPUTS_IC_1_BYTE, R27_ROUTING_MATRIX_INPUTS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_ROUTING_MATRIX_OUTPUTS_IC_1_ADDR, REG_ROUTING_MATRIX_OUTPUTS_IC_1_BYTE, R28_ROUTING_MATRIX_OUTPUTS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC_1_ADDR, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC_1_BYTE, R29_SERIAL_DATAGPIO_PIN_CONFIG_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DSP_SLEW_MODES_IC_1_ADDR, REG_DSP_SLEW_MODES_IC_1_BYTE, R30_DSP_SLEW_MODES_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC_1_ADDR, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC_1_BYTE, R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_CLOCK_ENABLE_REG_0_IC_1_ADDR , R32_CLOCK_ENABLE_REGISTERS_IC_1_SIZE, R32_CLOCK_ENABLE_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PARAM_ADDR_IC_1, PARAM_SIZE_IC_1, Param_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SAMPLE_RATE_SETTING_IC_1_ADDR, REG_SAMPLE_RATE_SETTING_IC_1_BYTE, R35_SAMPLE_RATE_SETTING_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DSP_RUN_REGISTER_IC_1_ADDR, REG_DSP_RUN_REGISTER_IC_1_BYTE, R36_DSP_RUN_REGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DEJITTER_REGISTER_CONTROL_IC_1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC_1_BYTE, R37_DEJITTER_REGISTER_CONTROL_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DEJITTER_REGISTER_CONTROL_IC_1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC_1_BYTE, R38_DEJITTER_REGISTER_CONTROL_IC_1_Default );
|
||||
}
|
||||
|
||||
#endif
|
||||
71
ADAU1761/System/H2201_V1_IC_1_PARAM.h
Normal file
71
ADAU1761/System/H2201_V1_IC_1_PARAM.h
Normal file
@@ -0,0 +1,71 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC_1_PARAM.h
|
||||
*
|
||||
* Created: Monday, April 25, 2022 11:45:56 AM
|
||||
* Description: H2201_V1:IC 1 parameter RAM definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __H2201_V1_IC_1_PARAM_H__
|
||||
#define __H2201_V1_IC_1_PARAM_H__
|
||||
|
||||
|
||||
/* Module Modulo Size - Modulo Size*/
|
||||
#define MOD_MODULOSIZE_COUNT 1
|
||||
#define MOD_MODULOSIZE_DEVICE "IC1"
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_ADDR 0
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_FIXPT 0x00001000
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(4096)
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
|
||||
/* Module NxM Mixer1 - NxM Mixer*/
|
||||
#define MOD_NXMMIXER1_COUNT 2
|
||||
#define MOD_NXMMIXER1_DEVICE "IC1"
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10000_ADDR 8
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10000_FIXPT 0x00800000
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10000_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10000_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10001_ADDR 9
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10001_FIXPT 0x00800000
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10001_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10001_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module NxM Mixer2 - NxM Mixer*/
|
||||
#define MOD_NXMMIXER2_COUNT 2
|
||||
#define MOD_NXMMIXER2_DEVICE "IC1"
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20000_ADDR 10
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20000_FIXPT 0x00800000
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20000_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20000_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20001_ADDR 11
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20001_FIXPT 0x00800000
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20001_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20001_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Single 1 - Single Volume*/
|
||||
#define MOD_SINGLE1_COUNT 1
|
||||
#define MOD_SINGLE1_DEVICE "IC1"
|
||||
#define MOD_SINGLE1_GAIN1940ALGNS1_ADDR 12
|
||||
#define MOD_SINGLE1_GAIN1940ALGNS1_FIXPT 0x00800000
|
||||
#define MOD_SINGLE1_GAIN1940ALGNS1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_SINGLE1_GAIN1940ALGNS1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Single 2 - Single Volume*/
|
||||
#define MOD_SINGLE2_COUNT 1
|
||||
#define MOD_SINGLE2_DEVICE "IC1"
|
||||
#define MOD_SINGLE2_GAIN1940ALGNS2_ADDR 13
|
||||
#define MOD_SINGLE2_GAIN1940ALGNS2_FIXPT 0x00800000
|
||||
#define MOD_SINGLE2_GAIN1940ALGNS2_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_SINGLE2_GAIN1940ALGNS2_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
#endif
|
||||
1049
ADAU1761/System/H2201_V1_IC_1_REG.h
Normal file
1049
ADAU1761/System/H2201_V1_IC_1_REG.h
Normal file
File diff suppressed because it is too large
Load Diff
52
ADAU1761/System/H2201_V1_NetList.xml
Normal file
52
ADAU1761/System/H2201_V1_NetList.xml
Normal file
@@ -0,0 +1,52 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!-- *
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright © 2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
-->
|
||||
<!--NetList XML file-->
|
||||
<NetList>
|
||||
<IC name=" IC 1 " type="DSPSigmaLP1">
|
||||
<Schematic>
|
||||
<Algorithm name="ICSigma200In1" friendlyname="Analog+Digital Inputs " cell="Input1 " location="{X=40, Y=304} " Growth="10 " GrowthB="0">
|
||||
<Link pin="O_C267_A0_P1_out" dir="out" link="Link2" />
|
||||
<Link pin="O_C267_A0_P2_out" dir="out" link="Link3" />
|
||||
<Link pin="O_C267_A0_P3_out" dir="out" link="Link4" />
|
||||
<Link pin="O_C267_A0_P4_out" dir="out" link="Link5" />
|
||||
</Algorithm>
|
||||
<Algorithm name="NxNMixer1940Alg1" friendlyname="NxM Ctrl Mixer " cell="NxM Mixer1 " location="{X=346, Y=205} " Growth="2 " GrowthB="1">
|
||||
<Link pin="I_C13_A0_P2_in" dir="in" link="Link2" />
|
||||
<Link pin="I_C13_A0_P3_in" dir="in" link="Link4" />
|
||||
<Link pin="O_C13_A0_P1_out" dir="out" link="Link7" />
|
||||
</Algorithm>
|
||||
<Algorithm name="NxNMixer1940Alg2" friendlyname="NxM Ctrl Mixer " cell="NxM Mixer2 " location="{X=350, Y=399} " Growth="2 " GrowthB="1">
|
||||
<Link pin="I_C19_A0_P2_in" dir="in" link="Link3" />
|
||||
<Link pin="I_C19_A0_P3_in" dir="in" link="Link5" />
|
||||
<Link pin="O_C19_A0_P1_out" dir="out" link="Link6" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS1" friendlyname="Gain (no slew) " cell="Single 1 " location="{X=808, Y=311} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C307_A0_P1_in" dir="in" link="Link6" />
|
||||
<Link pin="O_C307_A0_P2_out" dir="out" link="Link1" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS2" friendlyname="Gain (no slew) " cell="Single 2 " location="{X=821, Y=87} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C310_A0_P1_in" dir="in" link="Link7" />
|
||||
<Link pin="O_C310_A0_P2_out" dir="out" link="Link0" />
|
||||
</Algorithm>
|
||||
<Algorithm name="ICSigmaLP1Out1" friendlyname="1761 output " cell="Output1 " location="{X=972, Y=153} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C7_A0_P1_in" dir="in" link="Link0" />
|
||||
</Algorithm>
|
||||
<Algorithm name="ICSigmaLP1Out2" friendlyname="1761 output " cell="Output2 " location="{X=997, Y=375} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C76_A0_P1_in" dir="in" link="Link1" />
|
||||
</Algorithm>
|
||||
</Schematic>
|
||||
</IC>
|
||||
</NetList>
|
||||
39
ADAU1761/System/NumBytes_IC_1.dat
Normal file
39
ADAU1761/System/NumBytes_IC_1.dat
Normal file
@@ -0,0 +1,39 @@
|
||||
3,
|
||||
3,
|
||||
3,
|
||||
8,
|
||||
4,
|
||||
4,
|
||||
6,
|
||||
3,
|
||||
10,
|
||||
5,
|
||||
16,
|
||||
4,
|
||||
5,
|
||||
3,
|
||||
4,
|
||||
3,
|
||||
1022,
|
||||
1022,
|
||||
1022,
|
||||
1022,
|
||||
17,
|
||||
3,
|
||||
7,
|
||||
6,
|
||||
4,
|
||||
7,
|
||||
3,
|
||||
3,
|
||||
3,
|
||||
3,
|
||||
3,
|
||||
3,
|
||||
4,
|
||||
317,
|
||||
58,
|
||||
3,
|
||||
3,
|
||||
3,
|
||||
3,
|
||||
969
ADAU1761/System/TxBuffer_IC_1.dat
Normal file
969
ADAU1761/System/TxBuffer_IC_1.dat
Normal file
@@ -0,0 +1,969 @@
|
||||
0x40, 0xEB, /* (0) IC 1.Sample Rate Setting */
|
||||
0x7F,
|
||||
0x40, 0xF6, /* (1) IC 1.DSP Run Register */
|
||||
0x00,
|
||||
0x40, 0x00, /* (2) IC 1.Clock Control Register */
|
||||
0x0F,
|
||||
0x40, 0x02, /* (3) IC 1.PLL Control Register */
|
||||
0x00, 0x01, 0x00, 0x00, 0x20,
|
||||
0x03,
|
||||
0x00, 0x00, /* (4) IC 1.Delay */
|
||||
0x00, 0x64,
|
||||
0x40, 0x15, /* (5) IC 1.Serial Port Control Registers */
|
||||
0x00, 0x00,
|
||||
0x40, 0x11, /* (6) IC 1.ALC Control Registers */
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x40, 0x08, /* (7) IC 1.Microphone Control Register */
|
||||
0x00,
|
||||
0x40, 0x09, /* (8) IC 1.Record Input Signal Path Registers */
|
||||
0x00, 0x01, 0x05, 0x01, 0x05,
|
||||
0x00, 0x00, 0x08,
|
||||
0x40, 0x19, /* (9) IC 1.ADC Control Registers */
|
||||
0x13, 0x00, 0x00,
|
||||
0x40, 0x1C, /* (10) IC 1.Playback Output Signal Path Registers */
|
||||
0x61, 0x00, 0x61, 0x00, 0x0A,
|
||||
0x0A, 0x00, 0xE7, 0xE7, 0x02,
|
||||
0x02, 0xE7, 0x00, 0x03,
|
||||
0x40, 0x17, /* (11) IC 1.Converter Control Registers */
|
||||
0x00, 0x00,
|
||||
0x40, 0x2A, /* (12) IC 1.DAC Control Registers */
|
||||
0x03, 0x00, 0x00,
|
||||
0x40, 0x2D, /* (13) IC 1.Serial Port Pad Control Registers */
|
||||
0xAA,
|
||||
0x40, 0x2F, /* (14) IC 1.Communication Port Pad Control Registers */
|
||||
0xAA, 0x00,
|
||||
0x40, 0x31, /* (15) IC 1.Jack Detect Pad Control Register */
|
||||
0x08,
|
||||
0x08, 0x00, /* (16) Program Clear Block 0 */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x08, 0xCC, /* (17) Program Clear Block 1 */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x09, 0x98, /* (18) Program Clear Block 2 */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x0A, 0x64, /* (19) Program Clear Block 3 */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x0B, 0xFC, /* (20) Program Clear Block 4 */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x40, 0xF5, /* (21) IC 1.DSP ON Register */
|
||||
0x01,
|
||||
0x40, 0xC0, /* (22) IC 1.CRC Registers */
|
||||
0x7F, 0x7F, 0x60, 0x7F, 0x01,
|
||||
0x40, 0xC6, /* (23) IC 1.GPIO Registers */
|
||||
0x07, 0x07, 0x00, 0x00,
|
||||
0x40, 0xE9, /* (24) IC 1.Non Modulo Registers */
|
||||
0x10, 0x00,
|
||||
0x40, 0xD0, /* (25) IC 1.Watchdog Registers */
|
||||
0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x40, 0xEB, /* (26) IC 1.Sampling Rate Setting Register */
|
||||
0x7F,
|
||||
0x40, 0xF2, /* (27) IC 1.Routing Matrix Inputs Register */
|
||||
0x00,
|
||||
0x40, 0xF3, /* (28) IC 1.Routing Matrix Outputs Register */
|
||||
0x00,
|
||||
0x40, 0xF4, /* (29) IC 1.Serial Data Configuration Register */
|
||||
0x00,
|
||||
0x40, 0xF7, /* (30) IC 1.DSP Slew Mode Register */
|
||||
0x00,
|
||||
0x40, 0xF8, /* (31) IC 1.Serial Port Sample Rate Register */
|
||||
0x00,
|
||||
0x40, 0xF9, /* (32) IC 1.Clock Enable Registers */
|
||||
0x7F, 0x03,
|
||||
0x08, 0x00, /* (33) Program Data */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE0, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x34, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x2C, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x54, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x5C, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0xFF, 0x38, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x80, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE8, 0x0C, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x07, 0x20, 0x08,
|
||||
0x00, 0x00, 0x06, 0xA0, 0x00,
|
||||
0xFF, 0xE0, 0x00, 0xC0, 0x00,
|
||||
0xFF, 0x80, 0x07, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xC0, 0x22, 0x00, 0x27,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE8, 0x1E, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x01, 0x20, 0x00,
|
||||
0xFF, 0xD8, 0x01, 0x03, 0x00,
|
||||
0x00, 0x07, 0xC6, 0x00, 0x00,
|
||||
0xFF, 0x08, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xF4, 0x00, 0x20, 0x00,
|
||||
0xFF, 0xD8, 0x07, 0x02, 0x00,
|
||||
0xFD, 0xA5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x00, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0xAD, 0x08, 0x20, 0x00,
|
||||
0x00, 0x08, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x25, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x2D, 0x08, 0x20, 0x00,
|
||||
0x00, 0x18, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x09, 0x22, 0x00,
|
||||
0x00, 0x20, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x08, 0x0A, 0x20, 0x00,
|
||||
0x00, 0x18, 0x0B, 0x22, 0x00,
|
||||
0x00, 0x28, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x0C, 0x20, 0x00,
|
||||
0x00, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x20, 0x0D, 0x20, 0x00,
|
||||
0x00, 0x38, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x35, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xC0, 0x0F, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, /* (34) Param */
|
||||
0x00, 0x00, 0x10, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00, 0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00,
|
||||
0x80, 0x00, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00,
|
||||
0x40, 0xEB, /* (35) IC 1.Sample Rate Setting */
|
||||
0x00,
|
||||
0x40, 0xF6, /* (36) IC 1.DSP Run Register */
|
||||
0x01,
|
||||
0x40, 0x36, /* (37) IC 1.Dejitter Register Control */
|
||||
0x00,
|
||||
0x40, 0x36, /* (38) IC 1.Dejitter Register Control */
|
||||
0x03,
|
||||
26
ADAU1761/System/defines.h
Normal file
26
ADAU1761/System/defines.h
Normal file
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* File: defines.h
|
||||
*
|
||||
* Created: Monday, April 25, 2022 11:45:56 AM
|
||||
* Description: H2201_V1 IC default download data definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __DEFINES_H__
|
||||
#define __DEFINES_H__
|
||||
|
||||
#define BufferSize_IC_1 4625
|
||||
#define NumTransactions_IC_1 39
|
||||
|
||||
|
||||
#endif
|
||||
@@ -1,4 +1,4 @@
|
||||
idf_component_register(SRCS "bt_app_av.c"
|
||||
idf_component_register(SRCS "H2201_i2s.c" "bt_app_av.c"
|
||||
"bt_app_core.c"
|
||||
"main.c"
|
||||
INCLUDE_DIRS ".")
|
||||
|
||||
74
ESP32/main/H2201_i2s.c
Normal file
74
ESP32/main/H2201_i2s.c
Normal file
@@ -0,0 +1,74 @@
|
||||
// #include <stdint.h>
|
||||
// #include <string.h>
|
||||
// #include <stdbool.h>
|
||||
// #include "freertos/xtensa_api.h"
|
||||
// #include "freertos/FreeRTOSConfig.h"
|
||||
// #include "freertos/FreeRTOS.h"
|
||||
// #include "freertos/queue.h"
|
||||
// #include "freertos/task.h"
|
||||
// #include "esp_log.h"
|
||||
// //#include "bt_app_core.h"
|
||||
// #include "driver/i2s.h"
|
||||
// #include "freertos/ringbuf.h"
|
||||
|
||||
// #include "H2201_i2s.h"
|
||||
|
||||
// static xTaskHandle h2201_i2s_task_handle = NULL;
|
||||
// static RingbufHandle_t s_ringbuf_i2s = NULL;
|
||||
|
||||
// static void h2201_i2s_task(void *arg)
|
||||
// {
|
||||
// uint8_t *data = NULL;
|
||||
// size_t item_size = 0;
|
||||
// size_t bytes_written = 0;
|
||||
|
||||
// for (;;)
|
||||
// {
|
||||
// data = (uint8_t *)xRingbufferReceive(s_ringbuf_i2s, &item_size, (portTickType)portMAX_DELAY);
|
||||
// if (item_size != 0)
|
||||
// {
|
||||
// i2s_write(0, data, item_size, &bytes_written, portMAX_DELAY);
|
||||
// vRingbufferReturnItem(s_ringbuf_i2s, (void *)data);
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
|
||||
// void h2201_i2s_task_start_up(void)
|
||||
// {
|
||||
// s_ringbuf_i2s = xRingbufferCreate(8 * 1024, RINGBUF_TYPE_BYTEBUF);
|
||||
// if (s_ringbuf_i2s == NULL)
|
||||
// {
|
||||
// return;
|
||||
// }
|
||||
|
||||
// xTaskCreate(h2201_i2s_task, "BtI2ST", 1024, NULL, configMAX_PRIORITIES - 3, &h2201_i2s_task_handle);
|
||||
// return;
|
||||
// }
|
||||
|
||||
// void h2201_i2s_task_shut_down(void)
|
||||
// {
|
||||
// if (h2201_i2s_task_handle)
|
||||
// {
|
||||
// vTaskDelete(h2201_i2s_task_handle);
|
||||
// h2201_i2s_task_handle = NULL;
|
||||
// }
|
||||
|
||||
// if (s_ringbuf_i2s)
|
||||
// {
|
||||
// vRingbufferDelete(s_ringbuf_i2s);
|
||||
// s_ringbuf_i2s = NULL;
|
||||
// }
|
||||
// }
|
||||
|
||||
// size_t h2201_i2s_write_ringbuf(const uint8_t *data, size_t size)
|
||||
// {
|
||||
// BaseType_t done = xRingbufferSend(s_ringbuf_i2s, (void *)data, size, (portTickType)portMAX_DELAY);
|
||||
// if (done)
|
||||
// {
|
||||
// return size;
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// return 0;
|
||||
// }
|
||||
// }
|
||||
10
ESP32/main/H2201_i2s.h
Normal file
10
ESP32/main/H2201_i2s.h
Normal file
@@ -0,0 +1,10 @@
|
||||
// #ifndef __H2201_I2S_H__
|
||||
// #define __H2201_I2S_H__
|
||||
|
||||
// void h2201_i2s_task_start_up(void);
|
||||
|
||||
// void h2201_i2s_task_shut_down(void);
|
||||
|
||||
// size_t h2201_i2s_write_ringbuf(const uint8_t *data, size_t size);
|
||||
|
||||
// #endif /* __H2201_I2S_H__ */
|
||||
Reference in New Issue
Block a user