ACS/OPTA_CardController_mbed
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cleam up

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This commit is contained in:
Martijn Scheepers
2025-07-22 14:21:47 +02:00
parent d1ecebb941
commit cbce546cc1
9 changed files with 113 additions and 525 deletions
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1
custom_targets.json
View File

@@ -18,7 +18,6 @@
"clock_source": "USE_PLL_HSE_EXTC",
"lse_available": 1,
"lpticker_delay_ticks": 0,
"network-default-interface-type": "ETHERNET",
"i2c_timing_value_algo": true,
"hse_value": 25000000,
"enable-overdrive-mode": 0

16
framework-mbed/drivers/mbed_lib.json
View File

@@ -12,33 +12,33 @@
"crc-table-size": {
"macro_name": "MBED_CRC_TABLE_SIZE",
"help": "Number of entries in each of MbedCRC's pre-computed software tables. Higher values increase speed, but also increase image size. The value has no effect if the target performs the CRC in hardware. Permitted values are 0, 16 or 256.",
"value": 16
"value": 256
},
"spi_count_max": {
"spi-count-max": {
"help": "The maximum number of SPI peripherals used at the same time. Determines RAM allocated for SPI peripheral management. If null, limit determined by hardware.",
"value": null
},
"qspi_io0": {
"qspi-io0": {
"help": "QSPI data I/O 0 pin",
"value": "QSPI_FLASH1_IO0"
},
"qspi_io1": {
"qspi-io1": {
"help": "QSPI data I/O 1 pin",
"value": "QSPI_FLASH1_IO1"
},
"qspi_io2": {
"qspi-io2": {
"help": "QSPI data I/O 2 pin",
"value": "QSPI_FLASH1_IO2"
},
"qspi_io3": {
"qspi-io3": {
"help": "QSPI data I/O 3 pin",
"value": "QSPI_FLASH1_IO3"
},
"qspi_sck": {
"qspi-sck": {
"help": "QSPI clock pin",
"value": "QSPI_FLASH1_SCK"
},
"qspi_csn": {
"qspi-csn": {
"help": "QSPI chip select pin",
"value": "QSPI_FLASH1_CSN"
}

190
framework-mbed/hal/source/mbed_compat.c
View File

@@ -1,106 +1,106 @@
/* mbed Microcontroller Library
* Copyright (c) 2019 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// /* mbed Microcontroller Library
// * Copyright (c) 2019 ARM Limited
// * SPDX-License-Identifier: Apache-2.0
// *
// * Licensed under the Apache License, Version 2.0 (the "License");
// * you may not use this file except in compliance with the License.
// * You may obtain a copy of the License at
// *
// * http://www.apache.org/licenses/LICENSE-2.0
// *
// * Unless required by applicable law or agreed to in writing, software
// * distributed under the License is distributed on an "AS IS" BASIS,
// * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// * See the License for the specific language governing permissions and
// * limitations under the License.
// */
#include "analogin_api.h"
#include "i2c_api.h"
#include "spi_api.h"
#include "gpio_api.h"
#include "reset_reason_api.h"
#include "mbed_toolchain.h"
// #include "analogin_api.h"
// #include "i2c_api.h"
// #include "spi_api.h"
// #include "gpio_api.h"
// #include "reset_reason_api.h"
// #include "mbed_toolchain.h"
// To be re-implemented in the target layer if required
// MBED_WEAK void gpio_free(gpio_t *obj)
// {
// // Do nothing
// }
#if DEVICE_I2C
// To be re-implemented in the target layer if required
MBED_WEAK void i2c_free(i2c_t *obj)
{
// Do nothing
}
#endif
// #if DEVICE_ANALOGIN
// // To be re-implemented in the target layer if required
// MBED_WEAK void analogin_free(analogin_t *obj)
// // MBED_WEAK void gpio_free(gpio_t *obj)
// // {
// // // Do nothing
// // }
// #if DEVICE_I2C
// // To be re-implemented in the target layer if required
// MBED_WEAK void i2c_free(i2c_t *obj)
// {
// // Do nothing
// }
// #endif
// #if DEVICE_SPI
// // Default SPI capabilities. If specific target has different capabilities this function needs to be re-implemented.
// MBED_WEAK void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap)
// {
// if (slave) {
// cap->minimum_frequency = 200000; // 200 kHz
// cap->maximum_frequency = 2000000; // 2 MHz
// cap->word_length = 0x00008080; // 8 and 16 bit symbols
// cap->support_slave_mode = false; // to be determined later based on ssel
// cap->hw_cs_handle = false; // irrelevant in slave mode
// cap->slave_delay_between_symbols_ns = 2500; // 2.5 us
// cap->clk_modes = 0x0f; // all clock modes
// cap->tx_rx_buffers_equal_length = true; // rx buffer size must be equal tx buffer size
// #if DEVICE_SPI_ASYNCH
// cap->async_mode = true;
// #else
// cap->async_mode = false;
// #endif
// } else {
// cap->minimum_frequency = 200000; // 200 kHz
// cap->maximum_frequency = 2000000; // 2 MHz
// cap->word_length = 0x00008080; // 8 and 16 bit symbols
// cap->support_slave_mode = false; // to be determined later based on ssel
// cap->hw_cs_handle = false; // to be determined later based on ssel
// cap->slave_delay_between_symbols_ns = 0; // irrelevant in master mode
// cap->clk_modes = 0x0f; // all clock modes
// cap->tx_rx_buffers_equal_length = true; // rx buffer size must be equal tx buffer size
// #if DEVICE_SPI_ASYNCH
// cap->async_mode = true;
// #else
// cap->async_mode = false;
// #endif
// }
// // #if DEVICE_ANALOGIN
// // // To be re-implemented in the target layer if required
// // MBED_WEAK void analogin_free(analogin_t *obj)
// // {
// // // Do nothing
// // }
// // #endif
// // check if given ssel pin is in the cs pinmap
// const PinMap *cs_pins = spi_master_cs_pinmap();
// while (cs_pins->pin != NC) {
// if (cs_pins->pin == ssel) {
// #if DEVICE_SPISLAVE
// cap->support_slave_mode = true;
// #endif
// cap->hw_cs_handle = true;
// break;
// }
// cs_pins++;
// }
// }
// // #if DEVICE_SPI
// // // Default SPI capabilities. If specific target has different capabilities this function needs to be re-implemented.
// // MBED_WEAK void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap)
// // {
// // if (slave) {
// // cap->minimum_frequency = 200000; // 200 kHz
// // cap->maximum_frequency = 2000000; // 2 MHz
// // cap->word_length = 0x00008080; // 8 and 16 bit symbols
// // cap->support_slave_mode = false; // to be determined later based on ssel
// // cap->hw_cs_handle = false; // irrelevant in slave mode
// // cap->slave_delay_between_symbols_ns = 2500; // 2.5 us
// // cap->clk_modes = 0x0f; // all clock modes
// // cap->tx_rx_buffers_equal_length = true; // rx buffer size must be equal tx buffer size
// // #if DEVICE_SPI_ASYNCH
// // cap->async_mode = true;
// // #else
// // cap->async_mode = false;
// // #endif
// // } else {
// // cap->minimum_frequency = 200000; // 200 kHz
// // cap->maximum_frequency = 2000000; // 2 MHz
// // cap->word_length = 0x00008080; // 8 and 16 bit symbols
// // cap->support_slave_mode = false; // to be determined later based on ssel
// // cap->hw_cs_handle = false; // to be determined later based on ssel
// // cap->slave_delay_between_symbols_ns = 0; // irrelevant in master mode
// // cap->clk_modes = 0x0f; // all clock modes
// // cap->tx_rx_buffers_equal_length = true; // rx buffer size must be equal tx buffer size
// // #if DEVICE_SPI_ASYNCH
// // cap->async_mode = true;
// // #else
// // cap->async_mode = false;
// // #endif
// // }
// #endif
// // // check if given ssel pin is in the cs pinmap
// // const PinMap *cs_pins = spi_master_cs_pinmap();
// // while (cs_pins->pin != NC) {
// // if (cs_pins->pin == ssel) {
// // #if DEVICE_SPISLAVE
// // cap->support_slave_mode = true;
// // #endif
// // cap->hw_cs_handle = true;
// // break;
// // }
// // cs_pins++;
// // }
// // }
// #if DEVICE_RESET_REASON
// // To be re-implemented in the target layer if required
// MBED_WEAK void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap)
// {
// cap->reasons = (1 << RESET_REASON_PIN_RESET) | (1 << RESET_REASON_SOFTWARE);
// #if DEVICE_WATCHDOG
// cap->reasons |= 1 << RESET_REASON_WATCHDOG;
// #endif
// }
// #endif
// // #endif
// // #if DEVICE_RESET_REASON
// // // To be re-implemented in the target layer if required
// // MBED_WEAK void hal_reset_reason_get_capabilities(reset_reason_capabilities_t *cap)
// // {
// // cap->reasons = (1 << RESET_REASON_PIN_RESET) | (1 << RESET_REASON_SOFTWARE);
// // #if DEVICE_WATCHDOG
// // cap->reasons |= 1 << RESET_REASON_WATCHDOG;
// // #endif
// // }
// // #endif

67
framework-mbed/hal/usb/TARGET_Templates/USBPhyHw.h
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@@ -1,67 +0,0 @@
// /*
// * Copyright (c) 2018-2019, Arm Limited and affiliates.
// * SPDX-License-Identifier: Apache-2.0
// *
// * Licensed under the Apache License, Version 2.0 (the "License");
// * you may not use this file except in compliance with the License.
// * You may obtain a copy of the License at
// *
// * http://www.apache.org/licenses/LICENSE-2.0
// *
// * Unless required by applicable law or agreed to in writing, software
// * distributed under the License is distributed on an "AS IS" BASIS,
// * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// * See the License for the specific language governing permissions and
// * limitations under the License.
// */
// #ifndef USBPHYHW_H
// #define USBPHYHW_H
// #include "mbed.h"
// #include "USBPhy.h"
// class USBPhyHw : public USBPhy {
// public:
// USBPhyHw();
// virtual ~USBPhyHw();
// virtual void init(USBPhyEvents *events);
// virtual void deinit();
// virtual bool powered();
// virtual void connect();
// virtual void disconnect();
// virtual void configure();
// virtual void unconfigure();
// virtual void sof_enable();
// virtual void sof_disable();
// virtual void set_address(uint8_t address);
// virtual void remote_wakeup();
// virtual const usb_ep_table_t *endpoint_table();
// virtual uint32_t ep0_set_max_packet(uint32_t max_packet);
// virtual void ep0_setup_read_result(uint8_t *buffer, uint32_t size);
// virtual void ep0_read(uint8_t *data, uint32_t size);
// virtual uint32_t ep0_read_result();
// virtual void ep0_write(uint8_t *buffer, uint32_t size);
// virtual void ep0_stall();
// virtual bool endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type);
// virtual void endpoint_remove(usb_ep_t endpoint);
// virtual void endpoint_stall(usb_ep_t endpoint);
// virtual void endpoint_unstall(usb_ep_t endpoint);
// virtual bool endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size);
// virtual uint32_t endpoint_read_result(usb_ep_t endpoint);
// virtual bool endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size);
// virtual void endpoint_abort(usb_ep_t endpoint);
// virtual void process();
// private:
// USBPhyEvents *events;
// static void _usbisr(void);
// };
// #endif

311
framework-mbed/hal/usb/TARGET_Templates/USBPhy_template.cpp
View File

@@ -1,311 +0,0 @@
// /*
// * Copyright (c) 2018-2019, Arm Limited and affiliates.
// * SPDX-License-Identifier: Apache-2.0
// *
// * Licensed under the Apache License, Version 2.0 (the "License");
// * you may not use this file except in compliance with the License.
// * You may obtain a copy of the License at
// *
// * http://www.apache.org/licenses/LICENSE-2.0
// *
// * Unless required by applicable law or agreed to in writing, software
// * distributed under the License is distributed on an "AS IS" BASIS,
// * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// * See the License for the specific language governing permissions and
// * limitations under the License.
// */
// #include "USBPhyHw.h"
// static USBPhyHw *instance;
// USBPhy *get_usb_phy()
// {
// static USBPhyHw usbphy;
// return &usbphy;
// }
// USBPhyHw::USBPhyHw(): events(NULL)
// {
// }
// USBPhyHw::~USBPhyHw()
// {
// }
// void USBPhyHw::init(USBPhyEvents *events)
// {
// this->events = events;
// // Disable IRQ
// NVIC_DisableIRQ(USB_IRQn);
// // TODO - Setup clocks
// // TODO - Enable USB module
// // Enable IRQ
// NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
// NVIC_EnableIRQ(USB_IRQn);
// }
// void USBPhyHw::deinit()
// {
// // Disconnect and disable interrupt
// disconnect();
// NVIC_DisableIRQ(USB_IRQn);
// }
// bool USBPhyHw::powered()
// {
// // TODO - return true if powered false otherwise. Devices which don't support
// // this should always return true
// return true;
// }
// void USBPhyHw::connect()
// {
// // TODO - Enable endpoint interrupts
// // TODO - Enable pullup on D+
// }
// void USBPhyHw::disconnect()
// {
// // TODO - Disable all endpoints
// // TODO - Clear all endpoint interrupts
// // TODO - Disable pullup on D+
// }
// void USBPhyHw::configure()
// {
// // TODO - set device to configured. Most device will not need this
// }
// void USBPhyHw::unconfigure()
// {
// // TODO - set device to unconfigured. Most device will not need this
// }
// void USBPhyHw::sof_enable()
// {
// // TODO - Enable SOF interrupt
// }
// void USBPhyHw::sof_disable()
// {
// // TODO - Disable SOF interrupt
// }
// void USBPhyHw::set_address(uint8_t address)
// {
// // TODO - set the device address. Address must take effect
// // after the status phase of the current transfer
// }
// void USBPhyHw::remote_wakeup()
// {
// // TODO - Sent remote wakeup over USB lines (if supported)
// }
// const usb_ep_table_t *USBPhyHw::endpoint_table()
// {
// // TODO - Update the endpoint table for what your device supports
// static const usb_ep_table_t template_table = {
// 4096 - 32 * 4, // 32 words for endpoint buffers
// // +3 based added to interrupt and isochronous to ensure enough
// // space for 4 byte alignment
// {
// {USB_EP_ATTR_ALLOW_CTRL | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 0},
// {USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 3},
// {USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN_AND_OUT, 2, 0},
// {USB_EP_ATTR_ALLOW_ISO | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 3},
// {USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 3},
// {USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN_AND_OUT, 2, 0},
// {USB_EP_ATTR_ALLOW_ISO | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 3},
// {USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 3},
// {USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN_AND_OUT, 2, 0},
// {USB_EP_ATTR_ALLOW_ISO | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 3},
// {USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 3},
// {USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN_AND_OUT, 2, 0},
// {USB_EP_ATTR_ALLOW_ISO | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 3},
// {USB_EP_ATTR_ALLOW_INT | USB_EP_ATTR_DIR_IN_AND_OUT, 1, 3},
// {USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN_AND_OUT, 2, 0},
// {USB_EP_ATTR_ALLOW_BULK | USB_EP_ATTR_DIR_IN_AND_OUT, 2, 0}
// }
// };
// return &lpc_table;
// }
// uint32_t USBPhyHw::ep0_set_max_packet(uint32_t max_packet)
// {
// // TODO - set endpoint 0 size and return this size
// return 64;
// }
// // read setup packet
// void USBPhyHw::ep0_setup_read_result(uint8_t *buffer, uint32_t size)
// {
// // TODO - read up to size bytes of the setup packet
// }
// void USBPhyHw::ep0_read(uint8_t *data, uint32_t size)
// {
// // TODO - setup data buffer to receive next endpoint 0 OUT packet
// }
// uint32_t USBPhyHw::ep0_read_result()
// {
// // TODO - return the size of the last OUT packet received on endpoint 0
// return 0;
// }
// void USBPhyHw::ep0_write(uint8_t *buffer, uint32_t size)
// {
// // TODO - start transferring buffer on endpoint 0 IN
// }
// void USBPhyHw::ep0_stall()
// {
// // TODO - protocol stall endpoint 0. This stall must be automatically
// // cleared by the next setup packet
// }
// bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type)
// {
// // TODO - enable this endpoint
// return true;
// }
// void USBPhyHw::endpoint_remove(usb_ep_t endpoint)
// {
// // TODO - disable and remove this endpoint
// }
// void USBPhyHw::endpoint_stall(usb_ep_t endpoint)
// {
// // TODO - stall this endpoint until it is explicitly cleared
// }
// void USBPhyHw::endpoint_unstall(usb_ep_t endpoint)
// {
// // TODO - unstall this endpoint
// }
// bool USBPhyHw::endpoint_read(usb_ep_t endpoint, uint8_t *data, uint32_t size)
// {
// // TODO - setup data buffer to receive next endpoint OUT packet and return true if successful
// return true;
// }
// uint32_t USBPhyHw::endpoint_read_result(usb_ep_t endpoint)
// {
// // TODO - return the size of the last OUT packet received on endpoint
// }
// bool USBPhyHw::endpoint_write(usb_ep_t endpoint, uint8_t *data, uint32_t size)
// {
// // TODO - start transferring buffer on endpoint IN
// return true;
// }
// void USBPhyHw::endpoint_abort(usb_ep_t endpoint)
// {
// // TODO - stop the current transfer on this endpoint and don't call the IN or OUT callback
// }
// void USBPhyHw::process()
// {
// // TODO - update register for your mcu
// uint8_t stat = USB0->STAT;
// USB0->STAT = stat; // Clear pending interrupts
// // reset interrupt
// if (stat & USB_STAT_RESET_MASK) {
// // TODO - disable all endpoints
// // TODO - clear all endpoint interrupts
// // TODO - enable control endpoint
// // reset bus for USBDevice layer
// events->reset();
// // Re-enable interrupt
// NVIC_ClearPendingIRQ(USB_IRQn);
// NVIC_EnableIRQ(USB_IRQn);
// return;
// }
// // power applied
// if (stat & USB_STAT_POWERED) {
// events->powered(true);
// }
// // power lost
// if (stat & USB_STAT_UNPOWERED) {
// events->powered(false);
// }
// // sleep interrupt
// if (stat & USB_STAT_SUSPEND_MASK) {
// events->suspend(true);
// }
// // resume interrupt
// if (stat & USB_STAT_RESUME_MASK) {
// events->suspend(false);
// }
// // sof interrupt
// if (stat & USB_STAT_SOF_MASK) {
// // SOF event, read frame number
// events->sof(USB0->FRAME);
// }
// // endpoint interrupt
// if (stat & USB_STAT_EP_MASK) {
// uint32_t ep_pending = USB->EP;
// // TODO - call endpoint 0 IN callback if pending
// events->ep0_in();
// // TODO - call endpoint 0 OUT callback if pending
// events->ep0_out();
// // TODO - call endpoint 0 SETUP callback if pending
// events->ep0_setup();
// for (int i = 0; i < 16; i++) {
// // TODO - call endpoint i IN callback if pending
// events->in(0x80 | i);
// }
// for (int i = 0; i < 16; i++) {
// // TODO - call endpoint i OUT callback if pending
// events->out();
// }
// USB->EP = ep_pending; // clear pending
// }
// // Re-enable interrupt
// NVIC_ClearPendingIRQ(USB_IRQn);
// NVIC_EnableIRQ(USB_IRQn);
// }
// void USBPhyHw::_usbisr(void)
// {
// NVIC_DisableIRQ(USB_IRQn);
// instance->events->start_process();
// }

38
framework-mbed/storage/blockdevice/COMPONENT_QSPIF/mbed_lib.json
View File

@@ -3,7 +3,7 @@
"config": {
"enable-and-reset": {
"help": "(Legacy SFDP 1.0 ONLY) Reset sequence is enable reset (0x66) then reset (0x99)",
"value": false
"value": true
},
"direct-reset": {
"help": "(Legacy SFDP 1.0 ONLY) Reset involves a single command (0xF0)",
@@ -19,41 +19,9 @@
"QSPI_IO3": "MBED_CONF_DRIVERS_QSPI_IO3",
"QSPI_SCK": "MBED_CONF_DRIVERS_QSPI_SCK",
"QSPI_CSN": "MBED_CONF_DRIVERS_QSPI_CSN",
"QSPI_POLARITY_MODE": 0,
"QSPI_FREQ": "40000000",
"QSPI_POLARITY_MODE": 1,
"qspi-freq": "100000000",
"QSPI_MIN_READ_SIZE": "1",
"QSPI_MIN_PROG_SIZE": "1"
},
"target_overrides": {
"MX25R6435F": {
"QSPI_FREQ": "8000000",
"QSPI_NUM_STATUS_REGISTER":"3"
},
"MX25L51245G": {
"QSPI_FREQ": "8000000"
},
"MX25LM51245G": {
"QSPI_FREQ": "66000000"
},
"N25Q128A": {
"QSPI_FREQ": "80000000",
"enable-and-reset": true
},
"MCU_NRF52840": {
"QSPI_FREQ": "32000000",
"QSPI_MIN_READ_SIZE": "4",
"QSPI_MIN_PROG_SIZE": "4"
},
"MCU_PSOC6": {
"QSPI_FREQ": "50000000"
},
"EFM32GG11_STK3701": {
"QSPI_MIN_READ_SIZE": "4",
"QSPI_MIN_PROG_SIZE": "4"
},
"MCU_LPC546XX": {
"QSPI_MIN_READ_SIZE": "4",
"QSPI_MIN_PROG_SIZE": "4"
}
}
}

2
framework-mbed/targets/TARGET_STM/qspi_api.c
View File

@@ -41,6 +41,8 @@
/* When DACHE is available, DMA will be used when the buffer contains at least one cache-aligned block */
#define QSPI_DMA_THRESHOLD_BYTES 32
#if defined(QUADSPI)
static QSPI_HandleTypeDef *qspiHandle; // Handle of whatever QSPI structure is used for QUADSPI

8
framework-mbed/targets/targets.json
View File

@@ -181,7 +181,7 @@
"config": {
"clock_source": {
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
"value": "USE_PLL_HSE_EXTC",
"macro_name": "CLOCK_SOURCE"
},
"lpticker_lptim": {
@@ -196,7 +196,7 @@
"expected_value1": "PWR_LDO_SUPPLY | PWR_DIRECT_SMPS_SUPPLY",
"expected_value2": "PWR_SMPS_1V8_SUPPLIES_LDO | PWR_SMPS_2V5_SUPPLIES_LDO | PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO | PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO",
"expected_value3": "PWR_SMPS_1V8_SUPPLIES_EXT | PWR_SMPS_2V5_SUPPLIES_EXT | PWR_EXTERNAL_SOURCE_SUPPLY",
"value": "NC"
"value": "PWR_SMPS_1V8_SUPPLIES_LDO"
},
"i2c_timing_value_algo": {
"help": "If value was set to true I2C timing algorithm is enabled. Enabling may leads to performance issue. Keeping this false and changing system clock will trigger assert.)",
@@ -204,11 +204,11 @@
},
"enable-overdrive-mode": {
"help": "Enable 'overdrive mode' (also known as VOS0) and raise core clock to the maximum value. Only supported when the internal LDO is used for core voltage source. Reduces the temperature range of the chip, see datasheet for details.",
"value": 1
"value": 0
},
"hse_value": {
"help": "Frequency in MHz of external oscillator / crystal. Will be used to compute PLL parameters.",
"value": "8000000",
"value": "25000000",
"macro_name": "HSE_VALUE"
}
},

5
mbed_app.json
View File

@@ -23,10 +23,7 @@
"platform.memory-tracing-enabled": true,
"platform.error-filename-capture-enabled": true,
"rtos.main-thread-stack-size": 16384,
"qspif.enable-and-reset": true,
"qspif.num-status-register": 2,
"rtos.main-thread-stack-size": 16384,
"nsapi.socket-stats-enabled": false,