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support for h1502r10 and h1502r11

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This commit is contained in:
Martijn Scheepers
2017-10-20 09:19:19 +02:00
parent 94fd308940
commit 4331ad0b33
22 changed files with 1013 additions and 2 deletions
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4
build_h1502.sh → build_h1502r10.sh
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@@ -11,8 +11,8 @@ make clean
echo "----- make distclean -----"
make distclean
echo "----- make core9g25-128m-nf_defconfig -----"
make core9g25-128m-nf_defconfig
echo "----- make h1502r10-128m-nf_defconfig -----"
make h1502r10-128m-nf_defconfig
echo "----- make -----"
make

19
build_h1502r11.sh Executable file
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@@ -0,0 +1,19 @@
#!/bin/sh
export CROSS_COMPILE=arm-linux-gnueabi-
echo "----- make mrproper -----"
make mrproper
echo "----- make clean -----"
make clean
echo "----- make distclean -----"
make distclean
echo "----- make h1502r11-128m-nf_defconfig -----"
make h1502r11-128m-nf_defconfig
echo "----- make -----"
make

3
contrib/board/Config.in.board
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@@ -8,3 +8,6 @@ source "contrib/board/acme/sama5d3_acqua/Config.in.board"
source "contrib/board/acme/sama5d2_roadrunner/Config.in.board"
source "contrib/board/corewind/core9g25/Config.in.board"
source "contrib/board/axentia/sama5d3_linea/Config.in.board"
source "contrib/board/sdn/h1502r10/Config.in.board"
source "contrib/board/sdn/h1502r11/Config.in.board"

2
contrib/board/Config.in.boardname
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@@ -8,3 +8,5 @@ source "contrib/board/acme/sama5d3_acqua/Config.in.boardname"
source "contrib/board/acme/sama5d2_roadrunner/Config.in.boardname"
source "contrib/board/corewind/core9g25/Config.in.boardname"
source "contrib/board/axentia/sama5d3_linea/Config.in.boardname"
source "contrib/board/sdn/h1502r10/Config.in.boardname"
source "contrib/board/sdn/h1502r11/Config.in.boardname"

2
contrib/board/Config.in.linux_arg
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@@ -8,3 +8,5 @@ source "contrib/board/acme/sama5d3_acqua/Config.in.linux_arg"
source "contrib/board/acme/sama5d2_roadrunner/Config.in.linux_arg"
source "contrib/board/corewind/core9g25/Config.in.linux_arg"
source "contrib/board/axentia/sama5d3_linea/Config.in.linux_arg"
source "contrib/board/sdn/h1502r10/Config.in.linux_arg"
source "contrib/board/sdn/h1502r11/Config.in.linux_arg"

20
contrib/board/sdn/h1502r10/Config.in.board Normal file
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@@ -0,0 +1,20 @@
config CONFIG_H1502R10
bool "h1502r10"
select AT91SAM9X5
select CONFIG_DDRC
select ALLOW_DATAFLASH
select ALLOW_NANDFLASH
select ALLOW_SDCARD
select ALLOW_CPU_CLK_400MHZ
select ALLOW_CRYSTAL_12_000MHZ
select ALLOW_BOOT_FROM_DATAFLASH_CS0
select ALLOW_DATAFLASH_RECOVERY
select ALLOW_NANDFLASH_RECOVERY
select SUPPORT_BUS_SPEED_100MHZ
select SUPPORT_BUS_SPEED_133MHZ
select CONFIG_HAS_HW_INFO
select CONFIG_HAS_ONE_WIRE
help
Use the h1502r10 board

3
contrib/board/sdn/h1502r10/Config.in.boardname Normal file
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@@ -0,0 +1,3 @@
config CONFIG_BOARDNAME
default "h1502r10" if CONFIG_H1502R10

5
contrib/board/sdn/h1502r10/Config.in.linux_arg Normal file
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@@ -0,0 +1,5 @@
config CONFIG_LINUX_KERNEL_ARG_STRING
default "console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/kernel)ro,-(rootfs) rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs" if CONFIG_H1502R10 && !CONFIG_SDCARD
default "mem=128M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait" if CONFIG_H1502R10 && CONFIG_SDCARD && CONFIG_RAM_128MB

8
contrib/board/sdn/h1502r10/board.mk Normal file
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@@ -0,0 +1,8 @@
CPPFLAGS += \
-DCONFIG_H1502R10 \
-mcpu=arm926ej-s
ASFLAGS += \
-DCONFIG_H1502R10 \
-mcpu=arm926ej-s

11
contrib/board/sdn/h1502r10/h1502r10-128m-nf_defconfig Normal file
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@@ -0,0 +1,11 @@
CONFIG_H1502R10=y
CONFIG_RAM_128MB=y
CONFIG_NANDFLASH=y
# CONFIG_ONFI_DETECT_SUPPORT is not set
# CONFIG_USE_ON_DIE_ECC_SUPPORT is not set
CONFIG_DEBUG=y
CONFIG_THUMB=y
CONFIG_SCLK=y
# CONFIG_DISABLE_WATCHDOG is not set
# CONFIG_LOAD_ONE_WIRE is not set
CONFIG_NANDFLASH_RECOVERY

314
contrib/board/sdn/h1502r10/h1502r10.c Normal file
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@@ -0,0 +1,314 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "common.h"
#include "hardware.h"
#include "arch/at91_ccfg.h"
#include "arch/at91_rstc.h"
#include "arch/at91_pmc.h"
#include "arch/at91_smc.h"
#include "arch/at91_pio.h"
#include "arch/at91_ddrsdrc.h"
#include "gpio.h"
#include "pmc.h"
#include "usart.h"
#include "debug.h"
#include "ddramc.h"
#include "slowclk.h"
#include "timer.h"
#include "watchdog.h"
#include "string.h"
#include "board.h"
#include "h1502r10.h"
#ifdef CONFIG_USER_HW_INIT
extern void hw_init_hook(void);
#endif
static void at91_dbgu_hw_init(void)
{
/* Configure DBGU pins */
const struct pio_desc dbgu_pins[] = {
{"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pmc_enable_periph_clock(AT91C_ID_PIOA_B);
pio_configure(dbgu_pins);
}
static void initialize_dbgu(void)
{
at91_dbgu_hw_init();
usart_init(BAUDRATE(MASTER_CLOCK, BAUD_RATE));
}
#ifdef CONFIG_DDR2
/* Using the Micron MT47H64M16HR-3 */
static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS
| AT91C_DDRC2_MD_DDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 /* 10 column bits(1K) */
| AT91C_DDRC2_NR_13 /* 13 row bits (8K) */
| AT91C_DDRC2_CAS_3 /* CAS Latency 3 */
| AT91C_DDRC2_NB_BANKS_8 /* 8 banks */
| AT91C_DDRC2_DISABLE_RESET_DLL
| AT91C_DDRC2_DECOD_INTERLEAVED);/*Interleaved decode*/
/*
* The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
* With a 133 MHz frequency, the refresh timer count register must to be
* set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
* or (7.81 x 133 MHz) ~ 1040 i.e. 0x410.
*/
ddramc_config->rtr = 0x411; /* Refresh timer: 7.8125us */
/* One clock cycle @ 133 MHz = 7.5 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
| AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
| AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
| AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
| AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
| AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
| AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns*/
| AT91C_DDRC2_TRFC_(18)); /* 18 * 7.5 = 135 ns */
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(7) /* 7 * 7.5 = 52.5 ns */
| AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */
| AT91C_DDRC2_TRPA_(3) /* 3 * 7.5 = 22.5 ns */
| AT91C_DDRC2_TXARDS_(7) /* 7 clock cycles */
| AT91C_DDRC2_TXARD_(2)); /* 2 clock cycles */
}
static void ddramc_init(void)
{
unsigned long csa;
struct ddramc_register ddramc_reg;
ddramc_reg_config(&ddramc_reg);
/* ENABLE DDR2 clock */
pmc_enable_system_clock(AT91C_PMC_DDR);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
csa |= AT91C_EBI_CS1A_SDRAMC;
writel(csa, AT91C_BASE_CCFG + CCFG_EBICSA);
/* DDRAM2 Controller initialize */
ddram_initialize(AT91C_BASE_DDRSDRC, AT91C_BASE_CS1, &ddramc_reg);
}
#endif /* #ifdef CONFIG_DDR2 */
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
static void recovery_buttons_hw_init(void)
{
/* Configure recovery button PINs */
const struct pio_desc recovery_button_pins[] = {
{"RECOVERY_BUTTON", CONFIG_SYS_RECOVERY_BUTTON_PIN, 0, PIO_PULLUP, PIO_INPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_C},
};
pmc_enable_periph_clock(AT91C_ID_PIOC_D);
pio_configure(recovery_button_pins);
}
#endif /* #if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY) */
#ifdef CONFIG_HW_INIT
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator is
* supposed to be enabled PCK = MCK = MOSC
*/
pmc_init_pll(0);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Switch PCK/MCK on Main clock output */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
/* Switch PCK/MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/* Init timer */
timer_init();
#ifdef CONFIG_SCLK
slowclk_enable_osc32();
#endif
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_DDR2
/* Initialize DDRAM Controller */
ddramc_init();
#endif
/* one wire pin init */
//one_wire_hw_init();
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
}
#endif /* #ifdef CONFIG_HW_INIT */
#ifdef CONFIG_DATAFLASH
void at91_spi0_hw_init(void)
{
/* Configure PINs for SPI0 */
const struct pio_desc spi0_pins[] = {
{"MISO", AT91C_PIN_PA(11), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MOSI", AT91C_PIN_PA(12), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPCK", AT91C_PIN_PA(13), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pmc_enable_periph_clock(AT91C_ID_PIOA_B);
pio_configure(spi0_pins);
pmc_enable_periph_clock(AT91C_ID_SPI0);
}
#endif /* #ifdef CONFIG_DATAFLASH */
#ifdef CONFIG_SDCARD
#ifdef CONFIG_OF_LIBFDT
void at91_board_set_dtb_name(char *of_name)
{
strcpy(of_name, "core9g25");
strcat(of_name, ".dtb");
}
#endif
void at91_mci0_hw_init(void)
{
const struct pio_desc mci_pins[] = {
{"MCCK", AT91C_PIN_PA(17), 0, PIO_PULLUP, PIO_PERIPH_A},
{"MCCDA", AT91C_PIN_PA(16), 0, PIO_PULLUP, PIO_PERIPH_A},
{"MCDA0", AT91C_PIN_PA(15), 0, PIO_PULLUP, PIO_PERIPH_A},
{"MCDA1", AT91C_PIN_PA(18), 0, PIO_PULLUP, PIO_PERIPH_A},
{"MCDA2", AT91C_PIN_PA(19), 0, PIO_PULLUP, PIO_PERIPH_A},
{"MCDA3", AT91C_PIN_PA(20), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Configure the PIO controller */
pmc_enable_periph_clock(AT91C_ID_PIOA_B);
pio_configure(mci_pins);
/* Enable the clock */
pmc_enable_periph_clock(AT91C_ID_HSMCI0);
}
#endif /* #ifdef CONFIG_SDCARD */
#ifdef CONFIG_NANDFLASH
void nandflash_hw_init(void)
{
unsigned int reg;
/* Configure Nand PINs */
const struct pio_desc nand_pins_hi[] = {
{"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{"D0", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D1", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D2", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D3", AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D4", AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D5", AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D6", AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D7", AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
reg &= ~AT91C_EBI_DRV;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(1)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(2)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(3)
| AT91C_SMC_NCS_WRPULSE_(5)
| AT91C_SMC_NRDPULSE_(4)
| AT91C_SMC_NCS_RDPULSE_(6)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(7)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| AT91C_SMC_DBW_WIDTH_BITS_8
| AT91_SMC_TDF_(1)),
AT91C_BASE_SMC + SMC_CTRL3);
pio_configure(nand_pins_hi);
pmc_enable_periph_clock(AT91C_ID_PIOC_D);
}
#endif /* #ifdef CONFIG_NANDFLASH */

121
contrib/board/sdn/h1502r10/h1502r10.h Normal file
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@@ -0,0 +1,121 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2010, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __H1502R10_H__
#define __H1502R10_H__
/*
* PMC Settings
*
* The main oscillator is enabled as soon as possible in the lowlevel_clock_init
* and MCK is switched on the main oscillator.
* PLL initialization is done later in the hw_init() function
*/
#define MASTER_CLOCK 132096000
#define PLL_LOCK_TIMEOUT 10000
#define BAUD_RATE 115200
#define BOARD_MAINOSC 12000000
/* PCK = 396MHz, MCK = 132MHz */
#define PLLA_MULA 199
#define PLLA_DIVA 3
#define BOARD_MCK ((unsigned long)(((BOARD_MAINOSC / \
PLLA_DIVA) * (PLLA_MULA + 1)) / 2 / 3))
#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8))
#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0)
#define BOARD_PLLACOUNT (0x3F << 8)
#define BOARD_MULA (AT91C_CKGR_MULA & (PLLA_MULA << 16))
#define BOARD_DIVA (AT91C_CKGR_DIVA & PLLA_DIVA)
#define BOARD_PRESCALER_MAIN_CLOCK (AT91C_PMC_PLLADIV2_2 \
| AT91C_PMC_MDIV_3 \
| AT91C_PMC_CSS_MAIN_CLK)
#define BOARD_PRESCALER_PLLA (AT91C_PMC_PLLADIV2_2 \
| AT91C_PMC_MDIV_3 \
| AT91C_PMC_CSS_PLLA_CLK)
#define PLLA_SETTINGS (BOARD_CKGR_PLLA \
| BOARD_PLLACOUNT \
| BOARD_MULA \
| BOARD_DIVA)
#define PLLUTMI
#define PLLUTMI_SETTINGS 0x10193F05
/*
* DataFlash Settings
*/
#define CONFIG_SYS_SPI_CLOCK AT91C_SPI_CLK
#define CONFIG_SYS_SPI_MODE SPI_MODE3
#if defined(CONFIG_SPI_BUS0)
#define CONFIG_SYS_BASE_SPI AT91C_BASE_SPI0
#elif defined(CONFIG_SPI_BUS1)
#define CONFIG_SYS_BASE_SPI AT91C_BASE_SPI1
#endif
#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(14)
#elif (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(7)
#endif
/*
* NandFlash Settings
*/
#define CONFIG_SYS_NAND_BASE AT91C_BASE_CS3
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_OE_PIN AT91C_PIN_PD(0)
#define CONFIG_SYS_NAND_WE_PIN AT91C_PIN_PD(1)
#define CONFIG_SYS_NAND_ALE_PIN AT91C_PIN_PD(2)
#define CONFIG_SYS_NAND_CLE_PIN AT91C_PIN_PD(3)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91C_PIN_PD(4)
#define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET 0xC000
#define CONFIG_LOOKUP_TABLE_INDEX_OFFSET 0x8000
#define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET_1024 0x18000
#define CONFIG_LOOKUP_TABLE_INDEX_OFFSET_1024 0x10000
/*
* Recovery
*/
#define CONFIG_SYS_RECOVERY_BUTTON_PIN AT91C_PIN_PC(26)
#define RECOVERY_BUTTON_NAME "ESC"
/*
* MCI Settings
*/
#define CONFIG_SYS_BASE_MCI AT91C_BASE_HSMCI0
#endif /*#ifndef __CORE9G25_H__ */

20
contrib/board/sdn/h1502r11/Config.in.board Normal file
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@@ -0,0 +1,20 @@
config CONFIG_H1502R11
bool "h1502r11"
select AT91SAM9X5
select CONFIG_DDRC
select ALLOW_DATAFLASH
select ALLOW_NANDFLASH
select ALLOW_SDCARD
select ALLOW_CPU_CLK_400MHZ
select ALLOW_CRYSTAL_12_000MHZ
select ALLOW_BOOT_FROM_DATAFLASH_CS0
select ALLOW_DATAFLASH_RECOVERY
select ALLOW_NANDFLASH_RECOVERY
select SUPPORT_BUS_SPEED_100MHZ
select SUPPORT_BUS_SPEED_133MHZ
select CONFIG_HAS_HW_INFO
select CONFIG_HAS_ONE_WIRE
help
Use the h1502r11 board

3
contrib/board/sdn/h1502r11/Config.in.boardname Normal file
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@@ -0,0 +1,3 @@
config CONFIG_BOARDNAME
default "h1502r11" if CONFIG_H1502R11

5
contrib/board/sdn/h1502r11/Config.in.linux_arg Normal file
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@@ -0,0 +1,5 @@
config CONFIG_LINUX_KERNEL_ARG_STRING
default "console=ttyS0,115200 mtdparts=atmel_nand:8M(bootstrap/kernel)ro,-(rootfs) rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs" if CONFIG_H1502R11 && !CONFIG_SDCARD
default "mem=128M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait" if CONFIG_H1502R11 && CONFIG_SDCARD && CONFIG_RAM_128MB

8
contrib/board/sdn/h1502r11/board.mk Normal file
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@@ -0,0 +1,8 @@
CPPFLAGS += \
-DCONFIG_H1502R11 \
-mcpu=arm926ej-s
ASFLAGS += \
-DCONFIG_H1502R11 \
-mcpu=arm926ej-s

11
contrib/board/sdn/h1502r11/h1502r11-128m-nf_defconfig Normal file
View File

@@ -0,0 +1,11 @@
CONFIG_H1502R11=y
CONFIG_RAM_128MB=y
CONFIG_NANDFLASH=y
# CONFIG_ONFI_DETECT_SUPPORT is not set
# CONFIG_USE_ON_DIE_ECC_SUPPORT is not set
CONFIG_DEBUG=y
CONFIG_THUMB=y
CONFIG_SCLK=y
# CONFIG_DISABLE_WATCHDOG is not set
# CONFIG_LOAD_ONE_WIRE is not set
CONFIG_NANDFLASH_RECOVERY

316
contrib/board/sdn/h1502r11/h1502r11.c Normal file
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@@ -0,0 +1,316 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2008, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "common.h"
#include "hardware.h"
#include "arch/at91_ccfg.h"
#include "arch/at91_rstc.h"
#include "arch/at91_pmc.h"
#include "arch/at91_smc.h"
#include "arch/at91_pio.h"
#include "arch/at91_ddrsdrc.h"
#include "gpio.h"
#include "pmc.h"
#include "usart.h"
#include "debug.h"
#include "ddramc.h"
#include "slowclk.h"
#include "timer.h"
#include "watchdog.h"
#include "string.h"
#include "board.h"
#include "h1502r11.h"
#ifdef CONFIG_USER_HW_INIT
extern void hw_init_hook(void);
#endif
static void at91_dbgu_hw_init(void)
{
/* Configure DBGU pins */
const struct pio_desc dbgu_pins[] = {
{"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pmc_enable_periph_clock(AT91C_ID_PIOA_B);
pio_configure(dbgu_pins);
}
static void initialize_dbgu(void)
{
at91_dbgu_hw_init();
usart_init(BAUDRATE(MASTER_CLOCK, BAUD_RATE));
}
#ifdef CONFIG_DDR2
/* Using the Micron MT47H64M16HR-3 */
static void ddramc_reg_config(struct ddramc_register *ddramc_config)
{
ddramc_config->mdr = (AT91C_DDRC2_DBW_16_BITS
| AT91C_DDRC2_MD_DDR2_SDRAM);
ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9 /* 10 column bits(1K) */
| AT91C_DDRC2_NR_13 /* 13 row bits (8K) */
| AT91C_DDRC2_CAS_3 /* CAS Latency 3 */
| AT91C_DDRC2_NB_BANKS_8 /* 8 banks */
| AT91C_DDRC2_DISABLE_RESET_DLL
| AT91C_DDRC2_DECOD_INTERLEAVED);/*Interleaved decode*/
/*
* The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
* With a 133 MHz frequency, the refresh timer count register must to be
* set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
* or (7.81 x 133 MHz) ~ 1040 i.e. 0x410.
*/
ddramc_config->rtr = 0x411; /* Refresh timer: 7.8125us */
/* One clock cycle @ 133 MHz = 7.5 ns */
ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
| AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
| AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
| AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
| AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
| AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
| AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
| AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns*/
| AT91C_DDRC2_TRFC_(18)); /* 18 * 7.5 = 135 ns */
ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(7) /* 7 * 7.5 = 52.5 ns */
| AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */
| AT91C_DDRC2_TRPA_(3) /* 3 * 7.5 = 22.5 ns */
| AT91C_DDRC2_TXARDS_(7) /* 7 clock cycles */
| AT91C_DDRC2_TXARD_(2)); /* 2 clock cycles */
}
static void ddramc_init(void)
{
unsigned long csa;
struct ddramc_register ddramc_reg;
ddramc_reg_config(&ddramc_reg);
/* ENABLE DDR2 clock */
pmc_enable_system_clock(AT91C_PMC_DDR);
/* Chip select 1 is for DDR2/SDRAM */
csa = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
csa |= AT91C_EBI_CS1A_SDRAMC;
writel(csa, AT91C_BASE_CCFG + CCFG_EBICSA);
/* DDRAM2 Controller initialize */
ddram_initialize(AT91C_BASE_DDRSDRC, AT91C_BASE_CS1, &ddramc_reg);
}
#endif /* #ifdef CONFIG_DDR2 */
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
static void recovery_buttons_hw_init(void)
{
/* Configure recovery button PINs */
const struct pio_desc recovery_button_pins[] = {
{"RECOVERY_BUTTON", CONFIG_SYS_RECOVERY_BUTTON_PIN, 0, PIO_PULLUP, PIO_INPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_C},
};
pmc_enable_periph_clock(AT91C_ID_PIOC_D);
pio_configure(recovery_button_pins);
}
#endif /* #if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY) */
#ifdef CONFIG_HW_INIT
void hw_init(void)
{
/* Disable watchdog */
at91_disable_wdt();
/*
* At this stage the main oscillator is
* supposed to be enabled PCK = MCK = MOSC
*/
pmc_init_pll(0);
/* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
pmc_cfg_plla(PLLA_SETTINGS);
/* Switch PCK/MCK on Main clock output */
pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK);
/* Switch PCK/MCK on PLLA output */
pmc_cfg_mck(BOARD_PRESCALER_PLLA);
/* Enable External Reset */
writel(AT91C_RSTC_KEY_UNLOCK | AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR);
/* Init timer */
timer_init();
#ifdef CONFIG_SCLK
slowclk_enable_osc32();
#endif
/* Initialize dbgu */
initialize_dbgu();
#ifdef CONFIG_DDR2
/* Initialize DDRAM Controller */
ddramc_init();
#endif
/* one wire pin init */
//one_wire_hw_init();
#if defined(CONFIG_NANDFLASH_RECOVERY) || defined(CONFIG_DATAFLASH_RECOVERY)
/* Init the recovery buttons pins */
recovery_buttons_hw_init();
#endif
#ifdef CONFIG_USER_HW_INIT
hw_init_hook();
#endif
}
#endif /* #ifdef CONFIG_HW_INIT */
#ifdef CONFIG_DATAFLASH
void at91_spi0_hw_init(void)
{
/* Configure PINs for SPI0 */
const struct pio_desc spi0_pins[] = {
{"MISO", AT91C_PIN_PA(11), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"MOSI", AT91C_PIN_PA(12), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"SPCK", AT91C_PIN_PA(13), 0, PIO_DEFAULT, PIO_PERIPH_A},
{"NPCS", CONFIG_SYS_SPI_PCS, 1, PIO_DEFAULT, PIO_OUTPUT},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
pmc_enable_periph_clock(AT91C_ID_PIOA_B);
pio_configure(spi0_pins);
pmc_enable_periph_clock(AT91C_ID_SPI0);
}
#endif /* #ifdef CONFIG_DATAFLASH */
#ifdef CONFIG_SDCARD
#ifdef CONFIG_OF_LIBFDT
void at91_board_set_dtb_name(char *of_name)
{
strcpy(of_name, "core9g25");
strcat(of_name, ".dtb");
}
#endif
void at91_mci0_hw_init(void)
{
const struct pio_desc mci_pins[] = {
{"MCCK", AT91C_PIN_PA(17), 0, PIO_PULLUP, PIO_PERIPH_A},
{"MCCDA", AT91C_PIN_PA(16), 0, PIO_PULLUP, PIO_PERIPH_A},
{"MCDA0", AT91C_PIN_PA(15), 0, PIO_PULLUP, PIO_PERIPH_A},
{"MCDA1", AT91C_PIN_PA(18), 0, PIO_PULLUP, PIO_PERIPH_A},
{"MCDA2", AT91C_PIN_PA(19), 0, PIO_PULLUP, PIO_PERIPH_A},
{"MCDA3", AT91C_PIN_PA(20), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
/* Configure the PIO controller */
pmc_enable_periph_clock(AT91C_ID_PIOA_B);
pio_configure(mci_pins);
/* Enable the clock */
pmc_enable_periph_clock(AT91C_ID_HSMCI0);
}
#endif /* #ifdef CONFIG_SDCARD */
#ifdef CONFIG_NANDFLASH
void nandflash_hw_init(void)
{
unsigned int reg;
/* Configure Nand PINs */
const struct pio_desc nand_pins_hi[] = {
{"NANDOE", CONFIG_SYS_NAND_OE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDWE", CONFIG_SYS_NAND_WE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDALE", CONFIG_SYS_NAND_ALE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCLE", CONFIG_SYS_NAND_CLE_PIN, 0, PIO_PULLUP, PIO_PERIPH_A},
{"NANDCS", CONFIG_SYS_NAND_ENABLE_PIN, 1, PIO_PULLUP, PIO_OUTPUT},
{"D0", AT91C_PIN_PD(6), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D1", AT91C_PIN_PD(7), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D2", AT91C_PIN_PD(8), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D3", AT91C_PIN_PD(9), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D4", AT91C_PIN_PD(10), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D5", AT91C_PIN_PD(11), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D6", AT91C_PIN_PD(12), 0, PIO_PULLUP, PIO_PERIPH_A},
{"D7", AT91C_PIN_PD(13), 0, PIO_PULLUP, PIO_PERIPH_A},
{(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A},
};
reg = readl(AT91C_BASE_CCFG + CCFG_EBICSA);
reg |= AT91C_EBI_CS3A_SM;
reg |= (AT91C_EBI_DDR_MP_EN | AT91C_EBI_NFD0_ON_D16);
reg &= ~AT91C_EBI_DRV;
writel(reg, AT91C_BASE_CCFG + CCFG_EBICSA);
/* Configure SMC CS3 */
writel((AT91C_SMC_NWESETUP_(1)
| AT91C_SMC_NCS_WRSETUP_(0)
| AT91C_SMC_NRDSETUP_(2)
| AT91C_SMC_NCS_RDSETUP_(0)),
AT91C_BASE_SMC + SMC_SETUP3);
writel((AT91C_SMC_NWEPULSE_(3)
| AT91C_SMC_NCS_WRPULSE_(5)
| AT91C_SMC_NRDPULSE_(4)
| AT91C_SMC_NCS_RDPULSE_(6)),
AT91C_BASE_SMC + SMC_PULSE3);
writel((AT91C_SMC_NWECYCLE_(5)
| AT91C_SMC_NRDCYCLE_(7)),
AT91C_BASE_SMC + SMC_CYCLE3);
writel((AT91C_SMC_READMODE
| AT91C_SMC_WRITEMODE
| AT91C_SMC_NWAITM_NWAIT_DISABLE
| AT91C_SMC_DBW_WIDTH_BITS_8
| AT91_SMC_TDF_(1)),
AT91C_BASE_SMC + SMC_CTRL3);
pio_configure(nand_pins_hi);
pmc_enable_periph_clock(AT91C_ID_PIOC_D);
}
#endif /* #ifdef CONFIG_NANDFLASH */

121
contrib/board/sdn/h1502r11/h1502r11.h Normal file
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@@ -0,0 +1,121 @@
/* ----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support
* ----------------------------------------------------------------------------
* Copyright (c) 2010, Atmel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* - Redistributions of source code must retain the above copyright notice,
* this list of conditions and the disclaimer below.
*
* Atmel's name may not be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __H1502R11_H__
#define __H1502R11_H__
/*
* PMC Settings
*
* The main oscillator is enabled as soon as possible in the lowlevel_clock_init
* and MCK is switched on the main oscillator.
* PLL initialization is done later in the hw_init() function
*/
#define MASTER_CLOCK 132096000
#define PLL_LOCK_TIMEOUT 10000
#define BAUD_RATE 115200
#define BOARD_MAINOSC 12000000
/* PCK = 396MHz, MCK = 132MHz */
#define PLLA_MULA 199
#define PLLA_DIVA 3
#define BOARD_MCK ((unsigned long)(((BOARD_MAINOSC / \
PLLA_DIVA) * (PLLA_MULA + 1)) / 2 / 3))
#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8))
#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0)
#define BOARD_PLLACOUNT (0x3F << 8)
#define BOARD_MULA (AT91C_CKGR_MULA & (PLLA_MULA << 16))
#define BOARD_DIVA (AT91C_CKGR_DIVA & PLLA_DIVA)
#define BOARD_PRESCALER_MAIN_CLOCK (AT91C_PMC_PLLADIV2_2 \
| AT91C_PMC_MDIV_3 \
| AT91C_PMC_CSS_MAIN_CLK)
#define BOARD_PRESCALER_PLLA (AT91C_PMC_PLLADIV2_2 \
| AT91C_PMC_MDIV_3 \
| AT91C_PMC_CSS_PLLA_CLK)
#define PLLA_SETTINGS (BOARD_CKGR_PLLA \
| BOARD_PLLACOUNT \
| BOARD_MULA \
| BOARD_DIVA)
#define PLLUTMI
#define PLLUTMI_SETTINGS 0x10193F05
/*
* DataFlash Settings
*/
#define CONFIG_SYS_SPI_CLOCK AT91C_SPI_CLK
#define CONFIG_SYS_SPI_MODE SPI_MODE3
#if defined(CONFIG_SPI_BUS0)
#define CONFIG_SYS_BASE_SPI AT91C_BASE_SPI0
#elif defined(CONFIG_SPI_BUS1)
#define CONFIG_SYS_BASE_SPI AT91C_BASE_SPI1
#endif
#if (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS0_DATAFLASH)
#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(14)
#elif (AT91C_SPI_PCS_DATAFLASH == AT91C_SPI_PCS1_DATAFLASH)
#define CONFIG_SYS_SPI_PCS AT91C_PIN_PA(7)
#endif
/*
* NandFlash Settings
*/
#define CONFIG_SYS_NAND_BASE AT91C_BASE_CS3
#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
#define CONFIG_SYS_NAND_OE_PIN AT91C_PIN_PD(0)
#define CONFIG_SYS_NAND_WE_PIN AT91C_PIN_PD(1)
#define CONFIG_SYS_NAND_ALE_PIN AT91C_PIN_PD(2)
#define CONFIG_SYS_NAND_CLE_PIN AT91C_PIN_PD(3)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91C_PIN_PD(4)
#define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET 0xC000
#define CONFIG_LOOKUP_TABLE_INDEX_OFFSET 0x8000
#define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET_1024 0x18000
#define CONFIG_LOOKUP_TABLE_INDEX_OFFSET_1024 0x10000
/*
* Recovery
*/
#define CONFIG_SYS_RECOVERY_BUTTON_PIN AT91C_PIN_PA(21)
#define RECOVERY_BUTTON_NAME "CLR_MEM"
/*
* MCI Settings
*/
#define CONFIG_SYS_BASE_MCI AT91C_BASE_HSMCI0
#endif /*#ifndef __H1502R11_H__ */

8
contrib/include/contrib_board.h
View File

@@ -57,4 +57,12 @@
#include "sama5d3_linea.h"
#endif
#ifdef CONFIG_H1502R10
#include "h1502r10.h"
#endif
#ifdef CONFIG_H1502R11
#include "h1502r11.h"
#endif
#endif

7
defconfig Normal file
View File

@@ -0,0 +1,7 @@
CONFIG_CORE9G25=y
CONFIG_RAM_128MB=y
CONFIG_NANDFLASH=y
# CONFIG_ONFI_DETECT_SUPPORT is not set
# CONFIG_USE_ON_DIE_ECC_SUPPORT is not set
CONFIG_THUMB=y
# CONFIG_LOAD_ONE_WIRE is not set

4
scripts/addpmecchead.py
View File

@@ -19,6 +19,10 @@ elif sys.argv[3] == "at91sam9x5ek" or sys.argv[3] == "at91sam9n12ek":
pmecc_word = pmecc_head.gen_pmecc_header(2048, 64, 2, 512)
elif sys.argv[3] == "core9g25":
pmecc_word = pmecc_head.gen_pmecc_header(2048, 64, 2, 512)
elif sys.argv[3] == "h1502r10":
pmecc_word = pmecc_head.gen_pmecc_header(2048, 64, 2, 512)
elif sys.argv[3] == "h1502r11":
pmecc_word = pmecc_head.gen_pmecc_header(2048, 64, 2, 512)
else:
sys.exit("Not support board!")