I2c dsp setup
This commit is contained in:
Martijn Scheepers
Binary file not shown.
@@ -21,10 +21,10 @@ Beginning 19 19 0 1
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SafeLoadCode 15 15 0 7
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Input1 8 8 4 0
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End 5 5 0 0
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NxM Mixer2 3 3 1 2
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NxM Mixer1 3 3 1 2
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Single 2 3 3 1 1
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Single 1 3 3 1 1
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Right Mixer 3 3 1 2
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Left Mixer 3 3 1 2
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Left Master 3 3 1 1
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Right Master 3 3 1 1
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Output1 2 2 0 0
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Output2 2 2 0 0
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@@ -1,4 +1,4 @@
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Cell Name = Single 1
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Cell Name = Right Master
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Parameter Name = Gain1940AlgNS1
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Parameter Address = 12
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Parameter Value = 1
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@@ -7,7 +7,7 @@ Parameter Data :
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Cell Name = Single 2
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Cell Name = Left Master
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Parameter Name = Gain1940AlgNS2
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Parameter Address = 13
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Parameter Value = 1
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@@ -16,7 +16,7 @@ Parameter Data :
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Cell Name = NxM Mixer1
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Cell Name = Left Mixer
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Parameter Name = NxNMixer1940Alg1_00_00
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Parameter Address = 8
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Parameter Value = 1
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@@ -25,7 +25,7 @@ Parameter Data :
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Cell Name = NxM Mixer1
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Cell Name = Left Mixer
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Parameter Name = NxNMixer1940Alg1_00_01
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Parameter Address = 9
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Parameter Value = 1
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@@ -34,7 +34,7 @@ Parameter Data :
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Cell Name = NxM Mixer2
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Cell Name = Right Mixer
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Parameter Name = NxNMixer1940Alg2_00_00
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Parameter Address = 10
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Parameter Value = 1
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@@ -43,7 +43,7 @@ Parameter Data :
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Cell Name = NxM Mixer2
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Cell Name = Right Mixer
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Parameter Name = NxNMixer1940Alg2_00_01
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Parameter Address = 11
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Parameter Value = 1
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@@ -61,7 +61,7 @@ Parameter Data :
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Parameter data for: IC 1 (Hexadecimal format starting at parameter address 0)
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Parameter data for: IC1 (Hexadecimal format starting at parameter address 0)
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See also H2201_V1.hex file
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0x00 , 0x00 , 0x10 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 ,
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@@ -78,7 +78,7 @@ See also H2201_V1.hex file
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0x00 , 0x80 , 0x00 , 0x00 ,
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0x00 , 0x80 , 0x00 , 0x00 ,
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Parameter data for: IC 1 (Binary format starting at parameter address 0)
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Parameter data for: IC1 (Binary format starting at parameter address 0)
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00000000 00000000 00010000 00000000
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00000000 00000000 00000000 00000000
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00000000 00000000 00000000 00000000
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@@ -16,7 +16,7 @@
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<!--SigmaStudio export XML file-->
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<Schematic>
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<IC>
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<Name>IC 1</Name>
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<Name>IC1</Name>
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<PartNumber>DSPSigmaLP1</PartNumber>
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<Register>
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<Name>NonModRamAlloc</Name>
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@@ -26,112 +26,112 @@
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<Data>0x00, 0x00, 0x10, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Sample Rate Setting</Name>
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<Name>IC1.Sample Rate Setting</Name>
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<Address>0x40EB</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x7F, </Data>
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</Register>
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<Register>
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<Name>IC 1.DSP Run Register</Name>
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<Name>IC1.DSP Run Register</Name>
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<Address>0x40F6</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Clock Control Register</Name>
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<Name>IC1.Clock Control Register</Name>
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<Address>0x4000</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x0F, </Data>
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</Register>
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<Register>
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<Name>IC 1.PLL Control Register</Name>
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<Name>IC1.PLL Control Register</Name>
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<Address>0x4002</Address>
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<AddrIncr>0</AddrIncr>
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<Size>6</Size>
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<Data>0x00, 0x01, 0x00, 0x00, 0x20, 0x03, </Data>
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</Register>
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<Register>
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<Name>IC 1.Delay</Name>
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<Name>IC1.Delay</Name>
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<Address>0x0</Address>
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<AddrIncr>0</AddrIncr>
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<Size>2</Size>
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<Data>0x00, 0x64, </Data>
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</Register>
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<Register>
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<Name>IC 1.Serial Port Control Registers</Name>
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<Name>IC1.Serial Port Control Registers</Name>
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<Address>0x4015</Address>
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<AddrIncr>0</AddrIncr>
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<Size>2</Size>
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<Data>0x00, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.ALC Control Registers</Name>
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<Name>IC1.ALC Control Registers</Name>
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<Address>0x4011</Address>
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<AddrIncr>0</AddrIncr>
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<Size>4</Size>
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<Data>0x00, 0x00, 0x00, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Microphone Control Register</Name>
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<Name>IC1.Microphone Control Register</Name>
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<Address>0x4008</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Record Input Signal Path Registers</Name>
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<Name>IC1.Record Input Signal Path Registers</Name>
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<Address>0x4009</Address>
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<AddrIncr>0</AddrIncr>
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<Size>8</Size>
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<Data>0x00, 0x01, 0x05, 0x01, 0x05, 0x00, 0x00, 0x08, </Data>
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</Register>
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<Register>
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<Name>IC 1.ADC Control Registers</Name>
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<Name>IC1.ADC Control Registers</Name>
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<Address>0x4019</Address>
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<AddrIncr>0</AddrIncr>
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<Size>3</Size>
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<Data>0x13, 0x00, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Playback Output Signal Path Registers</Name>
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<Name>IC1.Playback Output Signal Path Registers</Name>
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<Address>0x401C</Address>
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<AddrIncr>0</AddrIncr>
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<Size>14</Size>
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<Data>0x61, 0x00, 0x61, 0x00, 0x0A, 0x0A, 0x00, 0xE7, 0xE7, 0x02, 0x02, 0xE7, 0x00, 0x03, </Data>
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</Register>
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<Register>
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<Name>IC 1.Converter Control Registers</Name>
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<Name>IC1.Converter Control Registers</Name>
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<Address>0x4017</Address>
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<AddrIncr>0</AddrIncr>
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<Size>2</Size>
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<Data>0x00, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.DAC Control Registers</Name>
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<Name>IC1.DAC Control Registers</Name>
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<Address>0x402A</Address>
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<AddrIncr>0</AddrIncr>
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<Size>3</Size>
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<Data>0x03, 0x00, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Serial Port Pad Control Registers</Name>
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<Name>IC1.Serial Port Pad Control Registers</Name>
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<Address>0x402D</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0xAA, </Data>
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</Register>
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<Register>
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<Name>IC 1.Communication Port Pad Control Registers</Name>
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<Name>IC1.Communication Port Pad Control Registers</Name>
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<Address>0x402F</Address>
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<AddrIncr>0</AddrIncr>
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<Size>2</Size>
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<Data>0xAA, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Jack Detect Pad Control Register</Name>
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<Name>IC1.Jack Detect Pad Control Register</Name>
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<Address>0x4031</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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@@ -173,84 +173,84 @@
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<Data>0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, </Data>
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</Program>
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<Register>
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<Name>IC 1.DSP ON Register</Name>
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<Name>IC1.DSP ON Register</Name>
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<Address>0x40F5</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x01, </Data>
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</Register>
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<Register>
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<Name>IC 1.CRC Registers</Name>
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<Name>IC1.CRC Registers</Name>
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<Address>0x40C0</Address>
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<AddrIncr>0</AddrIncr>
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<Size>5</Size>
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<Data>0x7F, 0x7F, 0x60, 0x7F, 0x01, </Data>
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</Register>
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<Register>
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<Name>IC 1.GPIO Registers</Name>
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<Name>IC1.GPIO Registers</Name>
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<Address>0x40C6</Address>
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<AddrIncr>0</AddrIncr>
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<Size>4</Size>
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<Data>0x07, 0x07, 0x00, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Non Modulo Registers</Name>
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<Name>IC1.Non Modulo Registers</Name>
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<Address>0x40E9</Address>
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<AddrIncr>0</AddrIncr>
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<Size>2</Size>
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<Data>0x10, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Watchdog Registers</Name>
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<Name>IC1.Watchdog Registers</Name>
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<Address>0x40D0</Address>
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<AddrIncr>0</AddrIncr>
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<Size>5</Size>
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<Data>0x00, 0x02, 0x00, 0x00, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Sampling Rate Setting Register</Name>
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<Name>IC1.Sampling Rate Setting Register</Name>
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<Address>0x40EB</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x7F, </Data>
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</Register>
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<Register>
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<Name>IC 1.Routing Matrix Inputs Register</Name>
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<Name>IC1.Routing Matrix Inputs Register</Name>
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<Address>0x40F2</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Routing Matrix Outputs Register</Name>
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<Name>IC1.Routing Matrix Outputs Register</Name>
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<Address>0x40F3</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Serial Data Configuration Register</Name>
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<Name>IC1.Serial Data Configuration Register</Name>
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<Address>0x40F4</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.DSP Slew Mode Register</Name>
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<Name>IC1.DSP Slew Mode Register</Name>
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<Address>0x40F7</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Serial Port Sample Rate Register</Name>
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<Name>IC1.Serial Port Sample Rate Register</Name>
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<Address>0x40F8</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Clock Enable Registers</Name>
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<Name>IC1.Clock Enable Registers</Name>
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<Address>0x40F9</Address>
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<AddrIncr>0</AddrIncr>
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<Size>2</Size>
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@@ -271,35 +271,35 @@
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<Data>0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Sample Rate Setting</Name>
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<Name>IC1.Sample Rate Setting</Name>
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<Address>0x40EB</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.DSP Run Register</Name>
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<Name>IC1.DSP Run Register</Name>
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<Address>0x40F6</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x01, </Data>
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</Register>
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<Register>
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<Name>IC 1.Dejitter Register Control</Name>
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<Name>IC1.Dejitter Register Control</Name>
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<Address>0x4036</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x00, </Data>
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</Register>
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<Register>
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<Name>IC 1.Dejitter Register Control</Name>
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<Name>IC1.Dejitter Register Control</Name>
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<Address>0x4036</Address>
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<AddrIncr>0</AddrIncr>
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<Size>1</Size>
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<Data>0x03, </Data>
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</Register>
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<Module>
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<CellName>Single 1</CellName>
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<CellName>Right Master</CellName>
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<Algorithm>
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<AlgoName>ALG0</AlgoName>
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<DetailedName>Gain1940AlgNS1</DetailedName>
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@@ -315,7 +315,7 @@
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</Algorithm>
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</Module>
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<Module>
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<CellName>Single 2</CellName>
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<CellName>Left Master</CellName>
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<Algorithm>
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<AlgoName>ALG0</AlgoName>
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<DetailedName>Gain1940AlgNS2</DetailedName>
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@@ -331,7 +331,7 @@
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</Algorithm>
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</Module>
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<Module>
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<CellName>NxM Mixer1</CellName>
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<CellName>Left Mixer</CellName>
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<Algorithm>
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<AlgoName>ALG0</AlgoName>
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<DetailedName>NxNMixer1940Alg1</DetailedName>
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@@ -355,7 +355,7 @@
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</Algorithm>
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</Module>
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<Module>
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<CellName>NxM Mixer2</CellName>
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<CellName>Right Mixer</CellName>
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<Algorithm>
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<AlgoName>ALG0</AlgoName>
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<DetailedName>NxNMixer1940Alg2</DetailedName>
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340
ADAU1761/System/H2201_V1_IC1.h
Normal file
340
ADAU1761/System/H2201_V1_IC1.h
Normal file
@@ -0,0 +1,340 @@
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/*
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* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC1.h
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*
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* Created: Tuesday, April 26, 2022 9:47:52 AM
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* Description: H2201_V1:IC1 program data.
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*
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* This software is distributed in the hope that it will be useful,
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* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
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* CONDITIONS OF ANY KIND, without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
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*
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* This software may only be used to program products purchased from
|
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* Analog Devices for incorporation by you into audio products that
|
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* are intended for resale to audio product end users. This software
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* may not be distributed whole or in any part to third parties.
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*
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* Copyright ©2022 Analog Devices, Inc. All rights reserved.
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*/
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#ifndef __H2201_V1_IC1_H__
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#define __H2201_V1_IC1_H__
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#include "SigmaStudioFW.h"
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#include "H2201_V1_IC1_REG.h"
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#define DEVICE_ARCHITECTURE_IC1 "ADAU176x"
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#define DEVICE_ADDR_IC1 0x70
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/* DSP Program Data */
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#define PROGRAM_SIZE_IC1 315
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#define PROGRAM_ADDR_IC1 2048
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ADI_REG_TYPE Program_Data_IC1[PROGRAM_SIZE_IC1] = {
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0x00, 0x00, 0x00, 0x00, 0x00,
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0xFE, 0xE0, 0x00, 0x00, 0x00,
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0xFF, 0x34, 0x00, 0x00, 0x00,
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0xFF, 0x2C, 0x00, 0x00, 0x00,
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0xFF, 0x54, 0x00, 0x00, 0x00,
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||||
0xFF, 0x5C, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
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||||
0xFF, 0x38, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x80, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE8, 0x0C, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x07, 0x20, 0x08,
|
||||
0x00, 0x00, 0x06, 0xA0, 0x00,
|
||||
0xFF, 0xE0, 0x00, 0xC0, 0x00,
|
||||
0xFF, 0x80, 0x07, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xC0, 0x22, 0x00, 0x27,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE8, 0x1E, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x01, 0x20, 0x00,
|
||||
0xFF, 0xD8, 0x01, 0x03, 0x00,
|
||||
0x00, 0x07, 0xC6, 0x00, 0x00,
|
||||
0xFF, 0x08, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xF4, 0x00, 0x20, 0x00,
|
||||
0xFF, 0xD8, 0x07, 0x02, 0x00,
|
||||
0xFD, 0xA5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x00, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0xAD, 0x08, 0x20, 0x00,
|
||||
0x00, 0x08, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x25, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x2D, 0x08, 0x20, 0x00,
|
||||
0x00, 0x18, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x09, 0x22, 0x00,
|
||||
0x00, 0x20, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x08, 0x0A, 0x20, 0x00,
|
||||
0x00, 0x18, 0x0B, 0x22, 0x00,
|
||||
0x00, 0x28, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x0C, 0x20, 0x00,
|
||||
0x00, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x20, 0x0D, 0x20, 0x00,
|
||||
0x00, 0x38, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x35, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xC0, 0x0F, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
};
|
||||
|
||||
/* DSP Parameter (Coefficient) Data */
|
||||
#define PARAM_SIZE_IC1 56
|
||||
#define PARAM_ADDR_IC1 0
|
||||
ADI_REG_TYPE Param_Data_IC1[PARAM_SIZE_IC1] = {
|
||||
0x00, 0x00, 0x10, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00, 0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00,
|
||||
0x80, 0x00, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00,
|
||||
};
|
||||
|
||||
|
||||
/* Register Default - IC1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R0_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x7F
|
||||
};
|
||||
|
||||
/* Register Default - IC1.DSP Run Register */
|
||||
ADI_REG_TYPE R1_DSP_RUN_REGISTER_IC1_Default[REG_DSP_RUN_REGISTER_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Clock Control Register */
|
||||
ADI_REG_TYPE R2_CLKCTRLREGISTER_IC1_Default[REG_CLKCTRLREGISTER_IC1_BYTE] = {
|
||||
0x0F
|
||||
};
|
||||
|
||||
/* Register Default - IC1.PLL Control Register */
|
||||
ADI_REG_TYPE R3_PLLCRLREGISTER_IC1_Default[REG_PLLCRLREGISTER_IC1_BYTE] = {
|
||||
0x00, 0x01, 0x00, 0x00, 0x20, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Delay */
|
||||
#define R4_DELAY_IC1_ADDR 0x0
|
||||
#define R4_DELAY_IC1_SIZE 2
|
||||
ADI_REG_TYPE R4_DELAY_IC1_Default[R4_DELAY_IC1_SIZE] = {
|
||||
0x00, 0x64
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Serial Port Control Registers */
|
||||
#define R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_Default[R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.ALC Control Registers */
|
||||
#define R6_ALC_CONTROL_REGISTERS_IC1_SIZE 4
|
||||
ADI_REG_TYPE R6_ALC_CONTROL_REGISTERS_IC1_Default[R6_ALC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Microphone Control Register */
|
||||
ADI_REG_TYPE R7_MICCTRLREGISTER_IC1_Default[REG_MICCTRLREGISTER_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Record Input Signal Path Registers */
|
||||
#define R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE 8
|
||||
ADI_REG_TYPE R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_Default[R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x01, 0x05, 0x01, 0x05, 0x00, 0x00, 0x08
|
||||
};
|
||||
|
||||
/* Register Default - IC1.ADC Control Registers */
|
||||
#define R9_ADC_CONTROL_REGISTERS_IC1_SIZE 3
|
||||
ADI_REG_TYPE R9_ADC_CONTROL_REGISTERS_IC1_Default[R9_ADC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x13, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Playback Output Signal Path Registers */
|
||||
#define R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE 14
|
||||
ADI_REG_TYPE R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_Default[R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE] = {
|
||||
0x61, 0x00, 0x61, 0x00, 0x0A, 0x0A, 0x00, 0xE7, 0xE7, 0x02, 0x02, 0xE7, 0x00, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Converter Control Registers */
|
||||
#define R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R11_CONVERTER_CONTROL_REGISTERS_IC1_Default[R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.DAC Control Registers */
|
||||
#define R12_DAC_CONTROL_REGISTERS_IC1_SIZE 3
|
||||
ADI_REG_TYPE R12_DAC_CONTROL_REGISTERS_IC1_Default[R12_DAC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x03, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Serial Port Pad Control Registers */
|
||||
#define R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE 1
|
||||
ADI_REG_TYPE R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_Default[R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0xAA
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Communication Port Pad Control Registers */
|
||||
#define R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_Default[R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0xAA, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Jack Detect Pad Control Register */
|
||||
ADI_REG_TYPE R15_JACKREGISTER_IC1_Default[REG_JACKREGISTER_IC1_BYTE] = {
|
||||
0x08
|
||||
};
|
||||
|
||||
/* Register Default - IC1.DSP ON Register */
|
||||
ADI_REG_TYPE R21_DSP_ENABLE_REGISTER_IC1_Default[REG_DSP_ENABLE_REGISTER_IC1_BYTE] = {
|
||||
0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC1.CRC Registers */
|
||||
#define R22_CRC_REGISTERS_IC1_SIZE 5
|
||||
ADI_REG_TYPE R22_CRC_REGISTERS_IC1_Default[R22_CRC_REGISTERS_IC1_SIZE] = {
|
||||
0x7F, 0x7F, 0x60, 0x7F, 0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC1.GPIO Registers */
|
||||
#define R23_GPIO_REGISTERS_IC1_SIZE 4
|
||||
ADI_REG_TYPE R23_GPIO_REGISTERS_IC1_Default[R23_GPIO_REGISTERS_IC1_SIZE] = {
|
||||
0x07, 0x07, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Non Modulo Registers */
|
||||
#define R24_NON_MODULO_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R24_NON_MODULO_REGISTERS_IC1_Default[R24_NON_MODULO_REGISTERS_IC1_SIZE] = {
|
||||
0x10, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Watchdog Registers */
|
||||
#define R25_WATCHDOG_REGISTERS_IC1_SIZE 5
|
||||
ADI_REG_TYPE R25_WATCHDOG_REGISTERS_IC1_Default[R25_WATCHDOG_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x02, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Sampling Rate Setting Register */
|
||||
ADI_REG_TYPE R26_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x7F
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Routing Matrix Inputs Register */
|
||||
ADI_REG_TYPE R27_ROUTING_MATRIX_INPUTS_IC1_Default[REG_ROUTING_MATRIX_INPUTS_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Routing Matrix Outputs Register */
|
||||
ADI_REG_TYPE R28_ROUTING_MATRIX_OUTPUTS_IC1_Default[REG_ROUTING_MATRIX_OUTPUTS_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Serial Data Configuration Register */
|
||||
ADI_REG_TYPE R29_SERIAL_DATAGPIO_PIN_CONFIG_IC1_Default[REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.DSP Slew Mode Register */
|
||||
ADI_REG_TYPE R30_DSP_SLEW_MODES_IC1_Default[REG_DSP_SLEW_MODES_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Serial Port Sample Rate Register */
|
||||
ADI_REG_TYPE R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_Default[REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Clock Enable Registers */
|
||||
#define R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R32_CLOCK_ENABLE_REGISTERS_IC1_Default[R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE] = {
|
||||
0x7F, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R35_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.DSP Run Register */
|
||||
ADI_REG_TYPE R36_DSP_RUN_REGISTER_IC1_Default[REG_DSP_RUN_REGISTER_IC1_BYTE] = {
|
||||
0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R37_DEJITTER_REGISTER_CONTROL_IC1_Default[REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R38_DEJITTER_REGISTER_CONTROL_IC1_Default[REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE] = {
|
||||
0x03
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Default Download
|
||||
*/
|
||||
#define DEFAULT_DOWNLOAD_SIZE_IC1 39
|
||||
|
||||
void default_download_IC1() {
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R0_SAMPLE_RATE_SETTING_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DSP_RUN_REGISTER_IC1_ADDR, REG_DSP_RUN_REGISTER_IC1_BYTE, R1_DSP_RUN_REGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_CLKCTRLREGISTER_IC1_ADDR, REG_CLKCTRLREGISTER_IC1_BYTE, R2_CLKCTRLREGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_PLLCRLREGISTER_IC1_ADDR, REG_PLLCRLREGISTER_IC1_BYTE, R3_PLLCRLREGISTER_IC1_Default );
|
||||
SIGMA_WRITE_DELAY( DEVICE_ADDR_IC1, R4_DELAY_IC1_SIZE, R4_DELAY_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SERIAL_PORT_CONTROL_0_IC1_ADDR , R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE, R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_ALC_CONTROL_0_IC1_ADDR , R6_ALC_CONTROL_REGISTERS_IC1_SIZE, R6_ALC_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_MICCTRLREGISTER_IC1_ADDR, REG_MICCTRLREGISTER_IC1_BYTE, R7_MICCTRLREGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_RECORD_PWR_MANAGEMENT_IC1_ADDR , R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE, R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_ADC_CONTROL_0_IC1_ADDR , R9_ADC_CONTROL_REGISTERS_IC1_SIZE, R9_ADC_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_PLAYBACK_MIXER_LEFT_CONTROL_0_IC1_ADDR , R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE, R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_CONVERTER_CTRL_0_IC1_ADDR , R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE, R11_CONVERTER_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DAC_CONTROL_0_IC1_ADDR , R12_DAC_CONTROL_REGISTERS_IC1_SIZE, R12_DAC_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SERIAL_PORT_PAD_CONTROL_0_IC1_ADDR , R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE, R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_COMM_PORT_PAD_CTRL_0_IC1_ADDR , R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE, R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_JACKREGISTER_IC1_ADDR, REG_JACKREGISTER_IC1_BYTE, R15_JACKREGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DSP_ENABLE_REGISTER_IC1_ADDR, REG_DSP_ENABLE_REGISTER_IC1_BYTE, R21_DSP_ENABLE_REGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_CRC_IDEAL_1_IC1_ADDR , R22_CRC_REGISTERS_IC1_SIZE, R22_CRC_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_GPIO_0_CONTROL_IC1_ADDR , R23_GPIO_REGISTERS_IC1_SIZE, R23_GPIO_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_NON_MODULO_RAM_1_IC1_ADDR , R24_NON_MODULO_REGISTERS_IC1_SIZE, R24_NON_MODULO_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_WATCHDOG_ENABLE_IC1_ADDR , R25_WATCHDOG_REGISTERS_IC1_SIZE, R25_WATCHDOG_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R26_SAMPLE_RATE_SETTING_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_ROUTING_MATRIX_INPUTS_IC1_ADDR, REG_ROUTING_MATRIX_INPUTS_IC1_BYTE, R27_ROUTING_MATRIX_INPUTS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_ROUTING_MATRIX_OUTPUTS_IC1_ADDR, REG_ROUTING_MATRIX_OUTPUTS_IC1_BYTE, R28_ROUTING_MATRIX_OUTPUTS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_ADDR, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_BYTE, R29_SERIAL_DATAGPIO_PIN_CONFIG_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DSP_SLEW_MODES_IC1_ADDR, REG_DSP_SLEW_MODES_IC1_BYTE, R30_DSP_SLEW_MODES_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_BYTE, R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_CLOCK_ENABLE_REG_0_IC1_ADDR , R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE, R32_CLOCK_ENABLE_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PARAM_ADDR_IC1, PARAM_SIZE_IC1, Param_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R35_SAMPLE_RATE_SETTING_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DSP_RUN_REGISTER_IC1_ADDR, REG_DSP_RUN_REGISTER_IC1_BYTE, R36_DSP_RUN_REGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DEJITTER_REGISTER_CONTROL_IC1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE, R37_DEJITTER_REGISTER_CONTROL_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DEJITTER_REGISTER_CONTROL_IC1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE, R38_DEJITTER_REGISTER_CONTROL_IC1_Default );
|
||||
}
|
||||
|
||||
#endif
|
||||
71
ADAU1761/System/H2201_V1_IC1_PARAM.h
Normal file
71
ADAU1761/System/H2201_V1_IC1_PARAM.h
Normal file
@@ -0,0 +1,71 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC1_PARAM.h
|
||||
*
|
||||
* Created: Tuesday, April 26, 2022 9:47:52 AM
|
||||
* Description: H2201_V1:IC1 parameter RAM definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __H2201_V1_IC1_PARAM_H__
|
||||
#define __H2201_V1_IC1_PARAM_H__
|
||||
|
||||
|
||||
/* Module Modulo Size - Modulo Size*/
|
||||
#define MOD_MODULOSIZE_COUNT 1
|
||||
#define MOD_MODULOSIZE_DEVICE "IC1"
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_ADDR 0
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_FIXPT 0x00001000
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(4096)
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
|
||||
/* Module Left Mixer - NxM Mixer*/
|
||||
#define MOD_LEFTMIXER_COUNT 2
|
||||
#define MOD_LEFTMIXER_DEVICE "IC1"
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_ADDR 8
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_FIXPT 0x00800000
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_ADDR 9
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_FIXPT 0x00800000
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Right Mixer - NxM Mixer*/
|
||||
#define MOD_RIGHTMIXER_COUNT 2
|
||||
#define MOD_RIGHTMIXER_DEVICE "IC1"
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_ADDR 10
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_ADDR 11
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Right Master - Single Volume*/
|
||||
#define MOD_RIGHTMASTER_COUNT 1
|
||||
#define MOD_RIGHTMASTER_DEVICE "IC1"
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_ADDR 12
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Left Master - Single Volume*/
|
||||
#define MOD_LEFTMASTER_COUNT 1
|
||||
#define MOD_LEFTMASTER_DEVICE "IC1"
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_ADDR 13
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_FIXPT 0x00800000
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
#endif
|
||||
1049
ADAU1761/System/H2201_V1_IC1_REG.h
Normal file
1049
ADAU1761/System/H2201_V1_IC1_REG.h
Normal file
File diff suppressed because it is too large
Load Diff
@@ -1,340 +0,0 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC_1.h
|
||||
*
|
||||
* Created: Monday, April 25, 2022 11:45:56 AM
|
||||
* Description: H2201_V1:IC 1 program data.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __H2201_V1_IC_1_H__
|
||||
#define __H2201_V1_IC_1_H__
|
||||
|
||||
#include "SigmaStudioFW.h"
|
||||
#include "H2201_V1_IC_1_REG.h"
|
||||
|
||||
#define DEVICE_ARCHITECTURE_IC_1 "ADAU176x"
|
||||
#define DEVICE_ADDR_IC_1 0x70
|
||||
|
||||
/* DSP Program Data */
|
||||
#define PROGRAM_SIZE_IC_1 315
|
||||
#define PROGRAM_ADDR_IC_1 2048
|
||||
ADI_REG_TYPE Program_Data_IC_1[PROGRAM_SIZE_IC_1] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE0, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x34, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x2C, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x54, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x5C, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0xFF, 0x38, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x80, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE8, 0x0C, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x07, 0x20, 0x08,
|
||||
0x00, 0x00, 0x06, 0xA0, 0x00,
|
||||
0xFF, 0xE0, 0x00, 0xC0, 0x00,
|
||||
0xFF, 0x80, 0x07, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xC0, 0x22, 0x00, 0x27,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE8, 0x1E, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x01, 0x20, 0x00,
|
||||
0xFF, 0xD8, 0x01, 0x03, 0x00,
|
||||
0x00, 0x07, 0xC6, 0x00, 0x00,
|
||||
0xFF, 0x08, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xF4, 0x00, 0x20, 0x00,
|
||||
0xFF, 0xD8, 0x07, 0x02, 0x00,
|
||||
0xFD, 0xA5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x00, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0xAD, 0x08, 0x20, 0x00,
|
||||
0x00, 0x08, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x25, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x2D, 0x08, 0x20, 0x00,
|
||||
0x00, 0x18, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x09, 0x22, 0x00,
|
||||
0x00, 0x20, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x08, 0x0A, 0x20, 0x00,
|
||||
0x00, 0x18, 0x0B, 0x22, 0x00,
|
||||
0x00, 0x28, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x0C, 0x20, 0x00,
|
||||
0x00, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x20, 0x0D, 0x20, 0x00,
|
||||
0x00, 0x38, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x35, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xC0, 0x0F, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
};
|
||||
|
||||
/* DSP Parameter (Coefficient) Data */
|
||||
#define PARAM_SIZE_IC_1 56
|
||||
#define PARAM_ADDR_IC_1 0
|
||||
ADI_REG_TYPE Param_Data_IC_1[PARAM_SIZE_IC_1] = {
|
||||
0x00, 0x00, 0x10, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00, 0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00,
|
||||
0x80, 0x00, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00,
|
||||
};
|
||||
|
||||
|
||||
/* Register Default - IC 1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R0_SAMPLE_RATE_SETTING_IC_1_Default[REG_SAMPLE_RATE_SETTING_IC_1_BYTE] = {
|
||||
0x7F
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.DSP Run Register */
|
||||
ADI_REG_TYPE R1_DSP_RUN_REGISTER_IC_1_Default[REG_DSP_RUN_REGISTER_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Clock Control Register */
|
||||
ADI_REG_TYPE R2_CLKCTRLREGISTER_IC_1_Default[REG_CLKCTRLREGISTER_IC_1_BYTE] = {
|
||||
0x0F
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.PLL Control Register */
|
||||
ADI_REG_TYPE R3_PLLCRLREGISTER_IC_1_Default[REG_PLLCRLREGISTER_IC_1_BYTE] = {
|
||||
0x00, 0x01, 0x00, 0x00, 0x20, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Delay */
|
||||
#define R4_DELAY_IC_1_ADDR 0x0
|
||||
#define R4_DELAY_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R4_DELAY_IC_1_Default[R4_DELAY_IC_1_SIZE] = {
|
||||
0x00, 0x64
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Serial Port Control Registers */
|
||||
#define R5_SERIAL_PORT_CONTROL_REGISTERS_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R5_SERIAL_PORT_CONTROL_REGISTERS_IC_1_Default[R5_SERIAL_PORT_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.ALC Control Registers */
|
||||
#define R6_ALC_CONTROL_REGISTERS_IC_1_SIZE 4
|
||||
ADI_REG_TYPE R6_ALC_CONTROL_REGISTERS_IC_1_Default[R6_ALC_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Microphone Control Register */
|
||||
ADI_REG_TYPE R7_MICCTRLREGISTER_IC_1_Default[REG_MICCTRLREGISTER_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Record Input Signal Path Registers */
|
||||
#define R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE 8
|
||||
ADI_REG_TYPE R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC_1_Default[R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE] = {
|
||||
0x00, 0x01, 0x05, 0x01, 0x05, 0x00, 0x00, 0x08
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.ADC Control Registers */
|
||||
#define R9_ADC_CONTROL_REGISTERS_IC_1_SIZE 3
|
||||
ADI_REG_TYPE R9_ADC_CONTROL_REGISTERS_IC_1_Default[R9_ADC_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0x13, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Playback Output Signal Path Registers */
|
||||
#define R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE 14
|
||||
ADI_REG_TYPE R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC_1_Default[R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE] = {
|
||||
0x61, 0x00, 0x61, 0x00, 0x0A, 0x0A, 0x00, 0xE7, 0xE7, 0x02, 0x02, 0xE7, 0x00, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Converter Control Registers */
|
||||
#define R11_CONVERTER_CONTROL_REGISTERS_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R11_CONVERTER_CONTROL_REGISTERS_IC_1_Default[R11_CONVERTER_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.DAC Control Registers */
|
||||
#define R12_DAC_CONTROL_REGISTERS_IC_1_SIZE 3
|
||||
ADI_REG_TYPE R12_DAC_CONTROL_REGISTERS_IC_1_Default[R12_DAC_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0x03, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Serial Port Pad Control Registers */
|
||||
#define R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE 1
|
||||
ADI_REG_TYPE R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC_1_Default[R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0xAA
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Communication Port Pad Control Registers */
|
||||
#define R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC_1_Default[R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE] = {
|
||||
0xAA, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Jack Detect Pad Control Register */
|
||||
ADI_REG_TYPE R15_JACKREGISTER_IC_1_Default[REG_JACKREGISTER_IC_1_BYTE] = {
|
||||
0x08
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.DSP ON Register */
|
||||
ADI_REG_TYPE R21_DSP_ENABLE_REGISTER_IC_1_Default[REG_DSP_ENABLE_REGISTER_IC_1_BYTE] = {
|
||||
0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.CRC Registers */
|
||||
#define R22_CRC_REGISTERS_IC_1_SIZE 5
|
||||
ADI_REG_TYPE R22_CRC_REGISTERS_IC_1_Default[R22_CRC_REGISTERS_IC_1_SIZE] = {
|
||||
0x7F, 0x7F, 0x60, 0x7F, 0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.GPIO Registers */
|
||||
#define R23_GPIO_REGISTERS_IC_1_SIZE 4
|
||||
ADI_REG_TYPE R23_GPIO_REGISTERS_IC_1_Default[R23_GPIO_REGISTERS_IC_1_SIZE] = {
|
||||
0x07, 0x07, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Non Modulo Registers */
|
||||
#define R24_NON_MODULO_REGISTERS_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R24_NON_MODULO_REGISTERS_IC_1_Default[R24_NON_MODULO_REGISTERS_IC_1_SIZE] = {
|
||||
0x10, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Watchdog Registers */
|
||||
#define R25_WATCHDOG_REGISTERS_IC_1_SIZE 5
|
||||
ADI_REG_TYPE R25_WATCHDOG_REGISTERS_IC_1_Default[R25_WATCHDOG_REGISTERS_IC_1_SIZE] = {
|
||||
0x00, 0x02, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Sampling Rate Setting Register */
|
||||
ADI_REG_TYPE R26_SAMPLE_RATE_SETTING_IC_1_Default[REG_SAMPLE_RATE_SETTING_IC_1_BYTE] = {
|
||||
0x7F
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Routing Matrix Inputs Register */
|
||||
ADI_REG_TYPE R27_ROUTING_MATRIX_INPUTS_IC_1_Default[REG_ROUTING_MATRIX_INPUTS_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Routing Matrix Outputs Register */
|
||||
ADI_REG_TYPE R28_ROUTING_MATRIX_OUTPUTS_IC_1_Default[REG_ROUTING_MATRIX_OUTPUTS_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Serial Data Configuration Register */
|
||||
ADI_REG_TYPE R29_SERIAL_DATAGPIO_PIN_CONFIG_IC_1_Default[REG_SERIAL_DATAGPIO_PIN_CONFIG_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.DSP Slew Mode Register */
|
||||
ADI_REG_TYPE R30_DSP_SLEW_MODES_IC_1_Default[REG_DSP_SLEW_MODES_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Serial Port Sample Rate Register */
|
||||
ADI_REG_TYPE R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC_1_Default[REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Clock Enable Registers */
|
||||
#define R32_CLOCK_ENABLE_REGISTERS_IC_1_SIZE 2
|
||||
ADI_REG_TYPE R32_CLOCK_ENABLE_REGISTERS_IC_1_Default[R32_CLOCK_ENABLE_REGISTERS_IC_1_SIZE] = {
|
||||
0x7F, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R35_SAMPLE_RATE_SETTING_IC_1_Default[REG_SAMPLE_RATE_SETTING_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.DSP Run Register */
|
||||
ADI_REG_TYPE R36_DSP_RUN_REGISTER_IC_1_Default[REG_DSP_RUN_REGISTER_IC_1_BYTE] = {
|
||||
0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R37_DEJITTER_REGISTER_CONTROL_IC_1_Default[REG_DEJITTER_REGISTER_CONTROL_IC_1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC 1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R38_DEJITTER_REGISTER_CONTROL_IC_1_Default[REG_DEJITTER_REGISTER_CONTROL_IC_1_BYTE] = {
|
||||
0x03
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Default Download
|
||||
*/
|
||||
#define DEFAULT_DOWNLOAD_SIZE_IC_1 39
|
||||
|
||||
void default_download_IC_1() {
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SAMPLE_RATE_SETTING_IC_1_ADDR, REG_SAMPLE_RATE_SETTING_IC_1_BYTE, R0_SAMPLE_RATE_SETTING_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DSP_RUN_REGISTER_IC_1_ADDR, REG_DSP_RUN_REGISTER_IC_1_BYTE, R1_DSP_RUN_REGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_CLKCTRLREGISTER_IC_1_ADDR, REG_CLKCTRLREGISTER_IC_1_BYTE, R2_CLKCTRLREGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_PLLCRLREGISTER_IC_1_ADDR, REG_PLLCRLREGISTER_IC_1_BYTE, R3_PLLCRLREGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_DELAY( DEVICE_ADDR_IC_1, R4_DELAY_IC_1_SIZE, R4_DELAY_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SERIAL_PORT_CONTROL_0_IC_1_ADDR , R5_SERIAL_PORT_CONTROL_REGISTERS_IC_1_SIZE, R5_SERIAL_PORT_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_ALC_CONTROL_0_IC_1_ADDR , R6_ALC_CONTROL_REGISTERS_IC_1_SIZE, R6_ALC_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_MICCTRLREGISTER_IC_1_ADDR, REG_MICCTRLREGISTER_IC_1_BYTE, R7_MICCTRLREGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_RECORD_PWR_MANAGEMENT_IC_1_ADDR , R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE, R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_ADC_CONTROL_0_IC_1_ADDR , R9_ADC_CONTROL_REGISTERS_IC_1_SIZE, R9_ADC_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_PLAYBACK_MIXER_LEFT_CONTROL_0_IC_1_ADDR , R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC_1_SIZE, R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_CONVERTER_CTRL_0_IC_1_ADDR , R11_CONVERTER_CONTROL_REGISTERS_IC_1_SIZE, R11_CONVERTER_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DAC_CONTROL_0_IC_1_ADDR , R12_DAC_CONTROL_REGISTERS_IC_1_SIZE, R12_DAC_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SERIAL_PORT_PAD_CONTROL_0_IC_1_ADDR , R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE, R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_COMM_PORT_PAD_CTRL_0_IC_1_ADDR , R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC_1_SIZE, R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_JACKREGISTER_IC_1_ADDR, REG_JACKREGISTER_IC_1_BYTE, R15_JACKREGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DSP_ENABLE_REGISTER_IC_1_ADDR, REG_DSP_ENABLE_REGISTER_IC_1_BYTE, R21_DSP_ENABLE_REGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_CRC_IDEAL_1_IC_1_ADDR , R22_CRC_REGISTERS_IC_1_SIZE, R22_CRC_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_GPIO_0_CONTROL_IC_1_ADDR , R23_GPIO_REGISTERS_IC_1_SIZE, R23_GPIO_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_NON_MODULO_RAM_1_IC_1_ADDR , R24_NON_MODULO_REGISTERS_IC_1_SIZE, R24_NON_MODULO_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_WATCHDOG_ENABLE_IC_1_ADDR , R25_WATCHDOG_REGISTERS_IC_1_SIZE, R25_WATCHDOG_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SAMPLE_RATE_SETTING_IC_1_ADDR, REG_SAMPLE_RATE_SETTING_IC_1_BYTE, R26_SAMPLE_RATE_SETTING_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_ROUTING_MATRIX_INPUTS_IC_1_ADDR, REG_ROUTING_MATRIX_INPUTS_IC_1_BYTE, R27_ROUTING_MATRIX_INPUTS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_ROUTING_MATRIX_OUTPUTS_IC_1_ADDR, REG_ROUTING_MATRIX_OUTPUTS_IC_1_BYTE, R28_ROUTING_MATRIX_OUTPUTS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC_1_ADDR, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC_1_BYTE, R29_SERIAL_DATAGPIO_PIN_CONFIG_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DSP_SLEW_MODES_IC_1_ADDR, REG_DSP_SLEW_MODES_IC_1_BYTE, R30_DSP_SLEW_MODES_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC_1_ADDR, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC_1_BYTE, R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_CLOCK_ENABLE_REG_0_IC_1_ADDR , R32_CLOCK_ENABLE_REGISTERS_IC_1_SIZE, R32_CLOCK_ENABLE_REGISTERS_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PROGRAM_ADDR_IC_1, PROGRAM_SIZE_IC_1, Program_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, PARAM_ADDR_IC_1, PARAM_SIZE_IC_1, Param_Data_IC_1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_SAMPLE_RATE_SETTING_IC_1_ADDR, REG_SAMPLE_RATE_SETTING_IC_1_BYTE, R35_SAMPLE_RATE_SETTING_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DSP_RUN_REGISTER_IC_1_ADDR, REG_DSP_RUN_REGISTER_IC_1_BYTE, R36_DSP_RUN_REGISTER_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DEJITTER_REGISTER_CONTROL_IC_1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC_1_BYTE, R37_DEJITTER_REGISTER_CONTROL_IC_1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC_1, REG_DEJITTER_REGISTER_CONTROL_IC_1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC_1_BYTE, R38_DEJITTER_REGISTER_CONTROL_IC_1_Default );
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,71 +0,0 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC_1_PARAM.h
|
||||
*
|
||||
* Created: Monday, April 25, 2022 11:45:56 AM
|
||||
* Description: H2201_V1:IC 1 parameter RAM definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __H2201_V1_IC_1_PARAM_H__
|
||||
#define __H2201_V1_IC_1_PARAM_H__
|
||||
|
||||
|
||||
/* Module Modulo Size - Modulo Size*/
|
||||
#define MOD_MODULOSIZE_COUNT 1
|
||||
#define MOD_MODULOSIZE_DEVICE "IC1"
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_ADDR 0
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_FIXPT 0x00001000
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(4096)
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
|
||||
/* Module NxM Mixer1 - NxM Mixer*/
|
||||
#define MOD_NXMMIXER1_COUNT 2
|
||||
#define MOD_NXMMIXER1_DEVICE "IC1"
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10000_ADDR 8
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10000_FIXPT 0x00800000
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10000_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10000_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10001_ADDR 9
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10001_FIXPT 0x00800000
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10001_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_NXMMIXER1_ALG0_NXNMIXER1940ALG10001_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module NxM Mixer2 - NxM Mixer*/
|
||||
#define MOD_NXMMIXER2_COUNT 2
|
||||
#define MOD_NXMMIXER2_DEVICE "IC1"
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20000_ADDR 10
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20000_FIXPT 0x00800000
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20000_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20000_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20001_ADDR 11
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20001_FIXPT 0x00800000
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20001_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_NXMMIXER2_ALG0_NXNMIXER1940ALG20001_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Single 1 - Single Volume*/
|
||||
#define MOD_SINGLE1_COUNT 1
|
||||
#define MOD_SINGLE1_DEVICE "IC1"
|
||||
#define MOD_SINGLE1_GAIN1940ALGNS1_ADDR 12
|
||||
#define MOD_SINGLE1_GAIN1940ALGNS1_FIXPT 0x00800000
|
||||
#define MOD_SINGLE1_GAIN1940ALGNS1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_SINGLE1_GAIN1940ALGNS1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Single 2 - Single Volume*/
|
||||
#define MOD_SINGLE2_COUNT 1
|
||||
#define MOD_SINGLE2_DEVICE "IC1"
|
||||
#define MOD_SINGLE2_GAIN1940ALGNS2_ADDR 13
|
||||
#define MOD_SINGLE2_GAIN1940ALGNS2_FIXPT 0x00800000
|
||||
#define MOD_SINGLE2_GAIN1940ALGNS2_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_SINGLE2_GAIN1940ALGNS2_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -15,7 +15,7 @@
|
||||
-->
|
||||
<!--NetList XML file-->
|
||||
<NetList>
|
||||
<IC name=" IC 1 " type="DSPSigmaLP1">
|
||||
<IC name=" IC1 " type="DSPSigmaLP1">
|
||||
<Schematic>
|
||||
<Algorithm name="ICSigma200In1" friendlyname="Analog+Digital Inputs " cell="Input1 " location="{X=40, Y=304} " Growth="10 " GrowthB="0">
|
||||
<Link pin="O_C267_A0_P1_out" dir="out" link="Link2" />
|
||||
@@ -23,21 +23,21 @@
|
||||
<Link pin="O_C267_A0_P3_out" dir="out" link="Link4" />
|
||||
<Link pin="O_C267_A0_P4_out" dir="out" link="Link5" />
|
||||
</Algorithm>
|
||||
<Algorithm name="NxNMixer1940Alg1" friendlyname="NxM Ctrl Mixer " cell="NxM Mixer1 " location="{X=346, Y=205} " Growth="2 " GrowthB="1">
|
||||
<Algorithm name="NxNMixer1940Alg1" friendlyname="NxM Ctrl Mixer " cell="Left Mixer " location="{X=346, Y=205} " Growth="2 " GrowthB="1">
|
||||
<Link pin="I_C13_A0_P2_in" dir="in" link="Link2" />
|
||||
<Link pin="I_C13_A0_P3_in" dir="in" link="Link4" />
|
||||
<Link pin="O_C13_A0_P1_out" dir="out" link="Link7" />
|
||||
</Algorithm>
|
||||
<Algorithm name="NxNMixer1940Alg2" friendlyname="NxM Ctrl Mixer " cell="NxM Mixer2 " location="{X=350, Y=399} " Growth="2 " GrowthB="1">
|
||||
<Algorithm name="NxNMixer1940Alg2" friendlyname="NxM Ctrl Mixer " cell="Right Mixer " location="{X=350, Y=399} " Growth="2 " GrowthB="1">
|
||||
<Link pin="I_C19_A0_P2_in" dir="in" link="Link3" />
|
||||
<Link pin="I_C19_A0_P3_in" dir="in" link="Link5" />
|
||||
<Link pin="O_C19_A0_P1_out" dir="out" link="Link6" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS1" friendlyname="Gain (no slew) " cell="Single 1 " location="{X=808, Y=311} " Growth="0 " GrowthB="0">
|
||||
<Algorithm name="Gain1940AlgNS1" friendlyname="Gain (no slew) " cell="Right Master " location="{X=808, Y=311} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C307_A0_P1_in" dir="in" link="Link6" />
|
||||
<Link pin="O_C307_A0_P2_out" dir="out" link="Link1" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS2" friendlyname="Gain (no slew) " cell="Single 2 " location="{X=821, Y=87} " Growth="0 " GrowthB="0">
|
||||
<Algorithm name="Gain1940AlgNS2" friendlyname="Gain (no slew) " cell="Left Master " location="{X=809, Y=87} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C310_A0_P1_in" dir="in" link="Link7" />
|
||||
<Link pin="O_C310_A0_P2_out" dir="out" link="Link0" />
|
||||
</Algorithm>
|
||||
|
||||
140
ADAU1761/System/SigmaStudioFW.h
Normal file
140
ADAU1761/System/SigmaStudioFW.h
Normal file
@@ -0,0 +1,140 @@
|
||||
/*
|
||||
* File: SigmaStudioFW.h
|
||||
*
|
||||
* Description: SigmaStudio System Framwork macro definitions. These
|
||||
* macros should be implemented for your system's software.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright © 2008 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __SIGMASTUDIOFW_H__
|
||||
#define __SIGMASTUDIOFW_H__
|
||||
|
||||
/*
|
||||
* TODO: Update for your system's data type
|
||||
*/
|
||||
typedef unsigned short ADI_DATA_U16;
|
||||
typedef unsigned char ADI_REG_TYPE;
|
||||
|
||||
extern vu16 Tx_Idx, Rx_Idx;
|
||||
extern vu16 NextBufferEnd, ThisBufferSize;
|
||||
extern u8 I2C1_Buffer_Tx[];
|
||||
#define Address_Length 2
|
||||
void SIGMA_WRITE_REGISTER_BLOCK(int devAddress, int address, int length, ADI_REG_TYPE *pData);
|
||||
void SIGMA_WRITE_DELAY(int devAddress, int length, ADI_REG_TYPE *pData );
|
||||
|
||||
|
||||
/*
|
||||
* Parameter data format
|
||||
*/
|
||||
#define SIGMASTUDIOTYPE_FIXPOINT 0
|
||||
#define SIGMASTUDIOTYPE_INTEGER 1
|
||||
|
||||
/*
|
||||
* Write to a single Device register
|
||||
*/
|
||||
#define SIGMA_WRITE_REGISTER( devAddress, address, dataLength, data ) {/*TODO: implement macro or define as function*/}
|
||||
|
||||
/*
|
||||
* TODO: CUSTOM MACRO IMPLEMENTATION
|
||||
* Write to multiple Device registers
|
||||
*/
|
||||
void SIGMA_WRITE_REGISTER_BLOCK(int devAddress, int address, int length, ADI_REG_TYPE *pData )
|
||||
{
|
||||
|
||||
int ii = 0;
|
||||
int zz = 0;
|
||||
Tx_Idx = 0;
|
||||
|
||||
/*----- Transmission Phase -----*/
|
||||
ThisBufferSize = Address_Length + length;
|
||||
|
||||
I2C1_Buffer_Tx[0] = (address & 0xFF00)>>8;
|
||||
I2C1_Buffer_Tx[1] = address & 0x00FF;
|
||||
|
||||
for(zz=0;zz<length;zz++)
|
||||
{
|
||||
I2C1_Buffer_Tx [zz + Address_Length] = pData[zz];
|
||||
}
|
||||
Tx_Idx = 0;
|
||||
for(ii =0;ii < ThisBufferSize;ii++)
|
||||
{
|
||||
|
||||
NextBufferEnd = ThisBufferSize;//I2C1_numbytes[ii];
|
||||
if(ii == 0) I2C_GenerateSTART(I2C1, ENABLE);
|
||||
/* Send data */
|
||||
while(Tx_Idx < NextBufferEnd)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void SIGMA_WRITE_DELAY(int devAddress, int length, ADI_REG_TYPE *pData )
|
||||
{
|
||||
// int cnt=0;
|
||||
int nCount=0;
|
||||
//int data_length = length - Address_Length;
|
||||
// ADI_REG_TYPE data[4]={0x05, 0xF5, 0xE1, 0x00};
|
||||
// for(cnt=0; cnt<data_length; cnt++)
|
||||
// {
|
||||
// nCount &= pData[cnt] >> (8*cnt);
|
||||
// }
|
||||
// for(cnt=0; cnt<4; cnt++)
|
||||
// {
|
||||
// nCount += data[cnt];
|
||||
// nCount = nCount<<(8);
|
||||
//
|
||||
// }
|
||||
//nCount=0xFFFFFF;
|
||||
//nCount=0x15752A00; //5 secs approx
|
||||
//nCount=0x05F5E100; //5 secs approx
|
||||
nCount=0xFFFFF;
|
||||
for(; nCount != 0; nCount--);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Read device registers
|
||||
*/
|
||||
#define SIGMA_READ_REGISTER( devAddress, address, length, pData ) {/*TODO: implement macro or define as function*/}
|
||||
|
||||
/*
|
||||
* Set a register field's value
|
||||
*/
|
||||
#define SIGMA_SET_REGSITER_FIELD( regVal, fieldVal, fieldMask, fieldShift ) \
|
||||
{ (regVal) = (((regVal) & (~(fieldMask))) | (((fieldVal) << (fieldShift)) && (fieldMask))) }
|
||||
|
||||
/*
|
||||
* Get the value of a register field
|
||||
*/
|
||||
#define SIGMA_GET_REGSITER_FIELD( regVal, fieldMask, fieldShift ) \
|
||||
{ ((regVal) & (fieldMask)) >> (fieldShift) }
|
||||
|
||||
/*
|
||||
* Convert a floating-point value to SigmaDSP (5.23) fixed point format
|
||||
* This optional macro is intended for systems having special implementation
|
||||
* requirements (for example: limited memory size or endianness)
|
||||
*/
|
||||
#define SIGMASTUDIOTYPE_FIXPOINT_CONVERT( _value ) {/*TODO: IMPLEMENT MACRO*/}
|
||||
|
||||
/*
|
||||
* Convert integer data to system compatible format
|
||||
* This optional macro is intended for systems having special implementation
|
||||
* requirements (for example: limited memory size or endianness)
|
||||
*/
|
||||
#define SIGMASTUDIOTYPE_INTEGER_CONVERT( _value ) {/*TODO: IMPLEMENT MACRO*/}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,38 +1,38 @@
|
||||
0x40, 0xEB, /* (0) IC 1.Sample Rate Setting */
|
||||
0x40, 0xEB, /* (0) IC1.Sample Rate Setting */
|
||||
0x7F,
|
||||
0x40, 0xF6, /* (1) IC 1.DSP Run Register */
|
||||
0x40, 0xF6, /* (1) IC1.DSP Run Register */
|
||||
0x00,
|
||||
0x40, 0x00, /* (2) IC 1.Clock Control Register */
|
||||
0x40, 0x00, /* (2) IC1.Clock Control Register */
|
||||
0x0F,
|
||||
0x40, 0x02, /* (3) IC 1.PLL Control Register */
|
||||
0x40, 0x02, /* (3) IC1.PLL Control Register */
|
||||
0x00, 0x01, 0x00, 0x00, 0x20,
|
||||
0x03,
|
||||
0x00, 0x00, /* (4) IC 1.Delay */
|
||||
0x00, 0x00, /* (4) IC1.Delay */
|
||||
0x00, 0x64,
|
||||
0x40, 0x15, /* (5) IC 1.Serial Port Control Registers */
|
||||
0x40, 0x15, /* (5) IC1.Serial Port Control Registers */
|
||||
0x00, 0x00,
|
||||
0x40, 0x11, /* (6) IC 1.ALC Control Registers */
|
||||
0x40, 0x11, /* (6) IC1.ALC Control Registers */
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x40, 0x08, /* (7) IC 1.Microphone Control Register */
|
||||
0x40, 0x08, /* (7) IC1.Microphone Control Register */
|
||||
0x00,
|
||||
0x40, 0x09, /* (8) IC 1.Record Input Signal Path Registers */
|
||||
0x40, 0x09, /* (8) IC1.Record Input Signal Path Registers */
|
||||
0x00, 0x01, 0x05, 0x01, 0x05,
|
||||
0x00, 0x00, 0x08,
|
||||
0x40, 0x19, /* (9) IC 1.ADC Control Registers */
|
||||
0x40, 0x19, /* (9) IC1.ADC Control Registers */
|
||||
0x13, 0x00, 0x00,
|
||||
0x40, 0x1C, /* (10) IC 1.Playback Output Signal Path Registers */
|
||||
0x40, 0x1C, /* (10) IC1.Playback Output Signal Path Registers */
|
||||
0x61, 0x00, 0x61, 0x00, 0x0A,
|
||||
0x0A, 0x00, 0xE7, 0xE7, 0x02,
|
||||
0x02, 0xE7, 0x00, 0x03,
|
||||
0x40, 0x17, /* (11) IC 1.Converter Control Registers */
|
||||
0x40, 0x17, /* (11) IC1.Converter Control Registers */
|
||||
0x00, 0x00,
|
||||
0x40, 0x2A, /* (12) IC 1.DAC Control Registers */
|
||||
0x40, 0x2A, /* (12) IC1.DAC Control Registers */
|
||||
0x03, 0x00, 0x00,
|
||||
0x40, 0x2D, /* (13) IC 1.Serial Port Pad Control Registers */
|
||||
0x40, 0x2D, /* (13) IC1.Serial Port Pad Control Registers */
|
||||
0xAA,
|
||||
0x40, 0x2F, /* (14) IC 1.Communication Port Pad Control Registers */
|
||||
0x40, 0x2F, /* (14) IC1.Communication Port Pad Control Registers */
|
||||
0xAA, 0x00,
|
||||
0x40, 0x31, /* (15) IC 1.Jack Detect Pad Control Register */
|
||||
0x40, 0x31, /* (15) IC1.Jack Detect Pad Control Register */
|
||||
0x08,
|
||||
0x08, 0x00, /* (16) Program Clear Block 0 */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
@@ -858,29 +858,29 @@
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x40, 0xF5, /* (21) IC 1.DSP ON Register */
|
||||
0x40, 0xF5, /* (21) IC1.DSP ON Register */
|
||||
0x01,
|
||||
0x40, 0xC0, /* (22) IC 1.CRC Registers */
|
||||
0x40, 0xC0, /* (22) IC1.CRC Registers */
|
||||
0x7F, 0x7F, 0x60, 0x7F, 0x01,
|
||||
0x40, 0xC6, /* (23) IC 1.GPIO Registers */
|
||||
0x40, 0xC6, /* (23) IC1.GPIO Registers */
|
||||
0x07, 0x07, 0x00, 0x00,
|
||||
0x40, 0xE9, /* (24) IC 1.Non Modulo Registers */
|
||||
0x40, 0xE9, /* (24) IC1.Non Modulo Registers */
|
||||
0x10, 0x00,
|
||||
0x40, 0xD0, /* (25) IC 1.Watchdog Registers */
|
||||
0x40, 0xD0, /* (25) IC1.Watchdog Registers */
|
||||
0x00, 0x02, 0x00, 0x00, 0x00,
|
||||
0x40, 0xEB, /* (26) IC 1.Sampling Rate Setting Register */
|
||||
0x40, 0xEB, /* (26) IC1.Sampling Rate Setting Register */
|
||||
0x7F,
|
||||
0x40, 0xF2, /* (27) IC 1.Routing Matrix Inputs Register */
|
||||
0x40, 0xF2, /* (27) IC1.Routing Matrix Inputs Register */
|
||||
0x00,
|
||||
0x40, 0xF3, /* (28) IC 1.Routing Matrix Outputs Register */
|
||||
0x40, 0xF3, /* (28) IC1.Routing Matrix Outputs Register */
|
||||
0x00,
|
||||
0x40, 0xF4, /* (29) IC 1.Serial Data Configuration Register */
|
||||
0x40, 0xF4, /* (29) IC1.Serial Data Configuration Register */
|
||||
0x00,
|
||||
0x40, 0xF7, /* (30) IC 1.DSP Slew Mode Register */
|
||||
0x40, 0xF7, /* (30) IC1.DSP Slew Mode Register */
|
||||
0x00,
|
||||
0x40, 0xF8, /* (31) IC 1.Serial Port Sample Rate Register */
|
||||
0x40, 0xF8, /* (31) IC1.Serial Port Sample Rate Register */
|
||||
0x00,
|
||||
0x40, 0xF9, /* (32) IC 1.Clock Enable Registers */
|
||||
0x40, 0xF9, /* (32) IC1.Clock Enable Registers */
|
||||
0x7F, 0x03,
|
||||
0x08, 0x00, /* (33) Program Data */
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
@@ -959,11 +959,11 @@
|
||||
0x80, 0x00, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00,
|
||||
0x40, 0xEB, /* (35) IC 1.Sample Rate Setting */
|
||||
0x40, 0xEB, /* (35) IC1.Sample Rate Setting */
|
||||
0x00,
|
||||
0x40, 0xF6, /* (36) IC 1.DSP Run Register */
|
||||
0x40, 0xF6, /* (36) IC1.DSP Run Register */
|
||||
0x01,
|
||||
0x40, 0x36, /* (37) IC 1.Dejitter Register Control */
|
||||
0x40, 0x36, /* (37) IC1.Dejitter Register Control */
|
||||
0x00,
|
||||
0x40, 0x36, /* (38) IC 1.Dejitter Register Control */
|
||||
0x40, 0x36, /* (38) IC1.Dejitter Register Control */
|
||||
0x03,
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* File: defines.h
|
||||
*
|
||||
* Created: Monday, April 25, 2022 11:45:56 AM
|
||||
* Created: Tuesday, April 26, 2022 9:47:52 AM
|
||||
* Description: H2201_V1 IC default download data definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
@@ -19,8 +19,8 @@
|
||||
#ifndef __DEFINES_H__
|
||||
#define __DEFINES_H__
|
||||
|
||||
#define BufferSize_IC_1 4625
|
||||
#define NumTransactions_IC_1 39
|
||||
#define BufferSize_IC1 4625
|
||||
#define NumTransactions_IC1 39
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
3
ESP32/.vscode/settings.json
vendored
3
ESP32/.vscode/settings.json
vendored
@@ -16,6 +16,7 @@
|
||||
"files.associations": {
|
||||
"esp_log.h": "c",
|
||||
"h2201_app.h": "c",
|
||||
"h2201_a2dp.h": "c"
|
||||
"h2201_a2dp.h": "c",
|
||||
"h2201_i2c.h": "c"
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
idf_component_register(SRCS "h2201_app.c" "H2201_avrcp.c" "H2201_a2dp.c" "H2201_i2s.c"
|
||||
idf_component_register(SRCS "H2201_i2c.c" "h2201_app.c" "H2201_avrcp.c" "H2201_a2dp.c" "H2201_i2s.c"
|
||||
|
||||
"main.c"
|
||||
INCLUDE_DIRS ".")
|
||||
|
||||
@@ -58,6 +58,7 @@ static void h2201_a2dp_eventhandler(uint16_t event, void *p_param)
|
||||
{
|
||||
ESP_LOGD(H2201_A2DP_TAG, "%s evt %d", __func__, event);
|
||||
esp_a2d_cb_param_t *a2d = NULL;
|
||||
|
||||
switch (event)
|
||||
{
|
||||
case ESP_A2D_CONNECTION_STATE_EVT:
|
||||
|
||||
603
ESP32/main/H2201_adau1761.h
Normal file
603
ESP32/main/H2201_adau1761.h
Normal file
@@ -0,0 +1,603 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC1.h
|
||||
*
|
||||
* Created: Tuesday, April 26, 2022 9:47:52 AM
|
||||
* Description: H2201_V1:IC1 program data.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __H2201_V1_IC1_H__
|
||||
#define __H2201_V1_IC1_H__
|
||||
|
||||
#include "SigmaStudioFW.h"
|
||||
#include "H2201_adau1761_reg.h"
|
||||
|
||||
#define DEVICE_ARCHITECTURE_IC1 "ADAU176x"
|
||||
#define DEVICE_ADDR_IC1 0x70
|
||||
|
||||
/* DSP Program Data */
|
||||
#define PROGRAM_SIZE_IC1 315
|
||||
#define PROGRAM_ADDR_IC1 2048
|
||||
ADI_REG_TYPE Program_Data_IC1[PROGRAM_SIZE_IC1] = {
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0xE0,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x34,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x2C,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x54,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x5C,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xF5,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x38,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0xE8,
|
||||
0x0C,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0x30,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xE8,
|
||||
0x07,
|
||||
0x20,
|
||||
0x08,
|
||||
0x00,
|
||||
0x00,
|
||||
0x06,
|
||||
0xA0,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xE0,
|
||||
0x00,
|
||||
0xC0,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x80,
|
||||
0x07,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0xC0,
|
||||
0x22,
|
||||
0x00,
|
||||
0x27,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0xE8,
|
||||
0x1E,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xE8,
|
||||
0x01,
|
||||
0x20,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xD8,
|
||||
0x01,
|
||||
0x03,
|
||||
0x00,
|
||||
0x00,
|
||||
0x07,
|
||||
0xC6,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x08,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xF4,
|
||||
0x00,
|
||||
0x20,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xD8,
|
||||
0x07,
|
||||
0x02,
|
||||
0x00,
|
||||
0xFD,
|
||||
0xA5,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0xFD,
|
||||
0xAD,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x08,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0xFD,
|
||||
0x25,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x10,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0xFD,
|
||||
0x2D,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x18,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x10,
|
||||
0x09,
|
||||
0x22,
|
||||
0x00,
|
||||
0x00,
|
||||
0x20,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x08,
|
||||
0x0A,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x18,
|
||||
0x0B,
|
||||
0x22,
|
||||
0x00,
|
||||
0x00,
|
||||
0x28,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x28,
|
||||
0x0C,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x30,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x20,
|
||||
0x0D,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x38,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x3D,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0xFD,
|
||||
0xB0,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x35,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0xFD,
|
||||
0xB8,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0x30,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0xC0,
|
||||
0x0F,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
};
|
||||
|
||||
/* DSP Parameter (Coefficient) Data */
|
||||
#define PARAM_SIZE_IC1 56
|
||||
#define PARAM_ADDR_IC1 0
|
||||
ADI_REG_TYPE Param_Data_IC1[PARAM_SIZE_IC1] = {
|
||||
0x00,
|
||||
0x00,
|
||||
0x10,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R0_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x7F};
|
||||
|
||||
/* Register Default - IC1.DSP Run Register */
|
||||
ADI_REG_TYPE R1_DSP_RUN_REGISTER_IC1_Default[REG_DSP_RUN_REGISTER_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Clock Control Register */
|
||||
ADI_REG_TYPE R2_CLKCTRLREGISTER_IC1_Default[REG_CLKCTRLREGISTER_IC1_BYTE] = {
|
||||
0x0F};
|
||||
|
||||
/* Register Default - IC1.PLL Control Register */
|
||||
ADI_REG_TYPE R3_PLLCRLREGISTER_IC1_Default[REG_PLLCRLREGISTER_IC1_BYTE] = {
|
||||
0x00, 0x01, 0x00, 0x00, 0x20, 0x03};
|
||||
|
||||
/* Register Default - IC1.Delay */
|
||||
#define R4_DELAY_IC1_ADDR 0x0
|
||||
#define R4_DELAY_IC1_SIZE 2
|
||||
ADI_REG_TYPE R4_DELAY_IC1_Default[R4_DELAY_IC1_SIZE] = {
|
||||
0x00, 0x64};
|
||||
|
||||
/* Register Default - IC1.Serial Port Control Registers */
|
||||
#define R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_Default[R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.ALC Control Registers */
|
||||
#define R6_ALC_CONTROL_REGISTERS_IC1_SIZE 4
|
||||
ADI_REG_TYPE R6_ALC_CONTROL_REGISTERS_IC1_Default[R6_ALC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.Microphone Control Register */
|
||||
ADI_REG_TYPE R7_MICCTRLREGISTER_IC1_Default[REG_MICCTRLREGISTER_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Record Input Signal Path Registers */
|
||||
#define R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE 8
|
||||
ADI_REG_TYPE R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_Default[R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x01, 0x05, 0x01, 0x05, 0x00, 0x00, 0x08};
|
||||
|
||||
/* Register Default - IC1.ADC Control Registers */
|
||||
#define R9_ADC_CONTROL_REGISTERS_IC1_SIZE 3
|
||||
ADI_REG_TYPE R9_ADC_CONTROL_REGISTERS_IC1_Default[R9_ADC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x13, 0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.Playback Output Signal Path Registers */
|
||||
#define R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE 14
|
||||
ADI_REG_TYPE R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_Default[R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE] = {
|
||||
0x61, 0x00, 0x61, 0x00, 0x0A, 0x0A, 0x00, 0xE7, 0xE7, 0x02, 0x02, 0xE7, 0x00, 0x03};
|
||||
|
||||
/* Register Default - IC1.Converter Control Registers */
|
||||
#define R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R11_CONVERTER_CONTROL_REGISTERS_IC1_Default[R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.DAC Control Registers */
|
||||
#define R12_DAC_CONTROL_REGISTERS_IC1_SIZE 3
|
||||
ADI_REG_TYPE R12_DAC_CONTROL_REGISTERS_IC1_Default[R12_DAC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x03, 0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.Serial Port Pad Control Registers */
|
||||
#define R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE 1
|
||||
ADI_REG_TYPE R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_Default[R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0xAA};
|
||||
|
||||
/* Register Default - IC1.Communication Port Pad Control Registers */
|
||||
#define R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_Default[R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0xAA, 0x00};
|
||||
|
||||
/* Register Default - IC1.Jack Detect Pad Control Register */
|
||||
ADI_REG_TYPE R15_JACKREGISTER_IC1_Default[REG_JACKREGISTER_IC1_BYTE] = {
|
||||
0x08};
|
||||
|
||||
/* Register Default - IC1.DSP ON Register */
|
||||
ADI_REG_TYPE R21_DSP_ENABLE_REGISTER_IC1_Default[REG_DSP_ENABLE_REGISTER_IC1_BYTE] = {
|
||||
0x01};
|
||||
|
||||
/* Register Default - IC1.CRC Registers */
|
||||
#define R22_CRC_REGISTERS_IC1_SIZE 5
|
||||
ADI_REG_TYPE R22_CRC_REGISTERS_IC1_Default[R22_CRC_REGISTERS_IC1_SIZE] = {
|
||||
0x7F, 0x7F, 0x60, 0x7F, 0x01};
|
||||
|
||||
/* Register Default - IC1.GPIO Registers */
|
||||
#define R23_GPIO_REGISTERS_IC1_SIZE 4
|
||||
ADI_REG_TYPE R23_GPIO_REGISTERS_IC1_Default[R23_GPIO_REGISTERS_IC1_SIZE] = {
|
||||
0x07, 0x07, 0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.Non Modulo Registers */
|
||||
#define R24_NON_MODULO_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R24_NON_MODULO_REGISTERS_IC1_Default[R24_NON_MODULO_REGISTERS_IC1_SIZE] = {
|
||||
0x10, 0x00};
|
||||
|
||||
/* Register Default - IC1.Watchdog Registers */
|
||||
#define R25_WATCHDOG_REGISTERS_IC1_SIZE 5
|
||||
ADI_REG_TYPE R25_WATCHDOG_REGISTERS_IC1_Default[R25_WATCHDOG_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x02, 0x00, 0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.Sampling Rate Setting Register */
|
||||
ADI_REG_TYPE R26_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x7F};
|
||||
|
||||
/* Register Default - IC1.Routing Matrix Inputs Register */
|
||||
ADI_REG_TYPE R27_ROUTING_MATRIX_INPUTS_IC1_Default[REG_ROUTING_MATRIX_INPUTS_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Routing Matrix Outputs Register */
|
||||
ADI_REG_TYPE R28_ROUTING_MATRIX_OUTPUTS_IC1_Default[REG_ROUTING_MATRIX_OUTPUTS_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Serial Data Configuration Register */
|
||||
ADI_REG_TYPE R29_SERIAL_DATAGPIO_PIN_CONFIG_IC1_Default[REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.DSP Slew Mode Register */
|
||||
ADI_REG_TYPE R30_DSP_SLEW_MODES_IC1_Default[REG_DSP_SLEW_MODES_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Serial Port Sample Rate Register */
|
||||
ADI_REG_TYPE R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_Default[REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Clock Enable Registers */
|
||||
#define R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R32_CLOCK_ENABLE_REGISTERS_IC1_Default[R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE] = {
|
||||
0x7F, 0x03};
|
||||
|
||||
/* Register Default - IC1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R35_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.DSP Run Register */
|
||||
ADI_REG_TYPE R36_DSP_RUN_REGISTER_IC1_Default[REG_DSP_RUN_REGISTER_IC1_BYTE] = {
|
||||
0x01};
|
||||
|
||||
/* Register Default - IC1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R37_DEJITTER_REGISTER_CONTROL_IC1_Default[REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R38_DEJITTER_REGISTER_CONTROL_IC1_Default[REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE] = {
|
||||
0x03};
|
||||
|
||||
/*
|
||||
* Default Download
|
||||
*/
|
||||
#define DEFAULT_DOWNLOAD_SIZE_IC1 39
|
||||
|
||||
void default_download_IC1()
|
||||
{
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R0_SAMPLE_RATE_SETTING_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DSP_RUN_REGISTER_IC1_ADDR, REG_DSP_RUN_REGISTER_IC1_BYTE, R1_DSP_RUN_REGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_CLKCTRLREGISTER_IC1_ADDR, REG_CLKCTRLREGISTER_IC1_BYTE, R2_CLKCTRLREGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_PLLCRLREGISTER_IC1_ADDR, REG_PLLCRLREGISTER_IC1_BYTE, R3_PLLCRLREGISTER_IC1_Default);
|
||||
SIGMA_WRITE_DELAY(DEVICE_ADDR_IC1, R4_DELAY_IC1_SIZE, R4_DELAY_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SERIAL_PORT_CONTROL_0_IC1_ADDR, R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE, R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_ALC_CONTROL_0_IC1_ADDR, R6_ALC_CONTROL_REGISTERS_IC1_SIZE, R6_ALC_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_MICCTRLREGISTER_IC1_ADDR, REG_MICCTRLREGISTER_IC1_BYTE, R7_MICCTRLREGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_RECORD_PWR_MANAGEMENT_IC1_ADDR, R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE, R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_ADC_CONTROL_0_IC1_ADDR, R9_ADC_CONTROL_REGISTERS_IC1_SIZE, R9_ADC_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_PLAYBACK_MIXER_LEFT_CONTROL_0_IC1_ADDR, R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE, R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_CONVERTER_CTRL_0_IC1_ADDR, R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE, R11_CONVERTER_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DAC_CONTROL_0_IC1_ADDR, R12_DAC_CONTROL_REGISTERS_IC1_SIZE, R12_DAC_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SERIAL_PORT_PAD_CONTROL_0_IC1_ADDR, R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE, R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_COMM_PORT_PAD_CTRL_0_IC1_ADDR, R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE, R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_JACKREGISTER_IC1_ADDR, REG_JACKREGISTER_IC1_BYTE, R15_JACKREGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DSP_ENABLE_REGISTER_IC1_ADDR, REG_DSP_ENABLE_REGISTER_IC1_BYTE, R21_DSP_ENABLE_REGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_CRC_IDEAL_1_IC1_ADDR, R22_CRC_REGISTERS_IC1_SIZE, R22_CRC_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_GPIO_0_CONTROL_IC1_ADDR, R23_GPIO_REGISTERS_IC1_SIZE, R23_GPIO_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_NON_MODULO_RAM_1_IC1_ADDR, R24_NON_MODULO_REGISTERS_IC1_SIZE, R24_NON_MODULO_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_WATCHDOG_ENABLE_IC1_ADDR, R25_WATCHDOG_REGISTERS_IC1_SIZE, R25_WATCHDOG_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R26_SAMPLE_RATE_SETTING_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_ROUTING_MATRIX_INPUTS_IC1_ADDR, REG_ROUTING_MATRIX_INPUTS_IC1_BYTE, R27_ROUTING_MATRIX_INPUTS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_ROUTING_MATRIX_OUTPUTS_IC1_ADDR, REG_ROUTING_MATRIX_OUTPUTS_IC1_BYTE, R28_ROUTING_MATRIX_OUTPUTS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_ADDR, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_BYTE, R29_SERIAL_DATAGPIO_PIN_CONFIG_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DSP_SLEW_MODES_IC1_ADDR, REG_DSP_SLEW_MODES_IC1_BYTE, R30_DSP_SLEW_MODES_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_BYTE, R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_CLOCK_ENABLE_REG_0_IC1_ADDR, R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE, R32_CLOCK_ENABLE_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PARAM_ADDR_IC1, PARAM_SIZE_IC1, Param_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R35_SAMPLE_RATE_SETTING_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DSP_RUN_REGISTER_IC1_ADDR, REG_DSP_RUN_REGISTER_IC1_BYTE, R36_DSP_RUN_REGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DEJITTER_REGISTER_CONTROL_IC1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE, R37_DEJITTER_REGISTER_CONTROL_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DEJITTER_REGISTER_CONTROL_IC1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE, R38_DEJITTER_REGISTER_CONTROL_IC1_Default);
|
||||
}
|
||||
|
||||
#endif
|
||||
1049
ESP32/main/H2201_adau1761_reg.h
Normal file
1049
ESP32/main/H2201_adau1761_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
194
ESP32/main/H2201_i2c.c
Normal file
194
ESP32/main/H2201_i2c.c
Normal file
@@ -0,0 +1,194 @@
|
||||
#include "esp_system.h"
|
||||
#include "esp_log.h"
|
||||
#include "driver/i2c.h"
|
||||
|
||||
#include "H2201_i2c.h"
|
||||
#include "H2201_adau1761.h"
|
||||
|
||||
void H2201_i2c_master_init(void)
|
||||
{
|
||||
i2c_config_t i2c_config = {
|
||||
.mode = I2C_MODE_MASTER,
|
||||
.sda_io_num = I2C_MASTER_SDA_IO,
|
||||
.sda_pullup_en = GPIO_PULLUP_DISABLE,
|
||||
.scl_io_num = I2C_MASTER_SCL_IO,
|
||||
.scl_pullup_en = GPIO_PULLUP_DISABLE,
|
||||
.master.clk_speed = I2C_MASTER_FREQ_HZ,
|
||||
// .clk_flags = 0, /*!< Optional, you can use I2C_SCLK_SRC_FLAG_* flags to choose i2c source clock here. */
|
||||
};
|
||||
esp_err_t err;
|
||||
if ((err = i2c_param_config(I2C_MASTER_NUM, &i2c_config)) != ESP_OK)
|
||||
{
|
||||
ESP_LOGE(H2201_I2C_TAG, "%s i2c param config failed: %s\n", __func__, esp_err_to_name(err));
|
||||
return;
|
||||
}
|
||||
if ((err = i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER, I2C_MASTER_RX_BUF_DISABLE, I2C_MASTER_TX_BUF_DISABLE, 0)) != ESP_OK)
|
||||
{
|
||||
ESP_LOGE(H2201_I2C_TAG, "%s i2c driver config failed: %s\n", __func__, esp_err_to_name(err));
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void H2201_i2c_adau1761_init(void)
|
||||
{
|
||||
default_download_IC1();
|
||||
|
||||
// i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
// i2c_master_start(cmd);
|
||||
|
||||
// i2c_master_write_byte(cmd, (OLED_I2C_ADDRESS << 1) | I2C_MASTER_WRITE, true);
|
||||
// i2c_master_write_byte(cmd, OLED_CONTROL_BYTE_CMD_STREAM, true);
|
||||
|
||||
// i2c_master_write_byte(cmd, OLED_CMD_SET_CHARGE_PUMP, true);
|
||||
// i2c_master_write_byte(cmd, 0x14, true);
|
||||
|
||||
// i2c_master_write_byte(cmd, OLED_CMD_SET_SEGMENT_REMAP, true); // reverse left-right mapping
|
||||
// i2c_master_write_byte(cmd, OLED_CMD_SET_COM_SCAN_MODE, true); // reverse up-bottom mapping
|
||||
|
||||
// i2c_master_write_byte(cmd, OLED_CMD_DISPLAY_ON, true);
|
||||
// i2c_master_stop(cmd);
|
||||
|
||||
// esp_err_t err = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 10 / portTICK_PERIOD_MS);
|
||||
// if (err == ESP_OK)
|
||||
// {
|
||||
// ESP_LOGI(H2201_I2C_TAG, "ADAU1761 configured successfully");
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// ESP_LOGE(H2201_I2C_TAG, "ADAU1761 configuration failed. code: 0x%.2X", err);
|
||||
// }
|
||||
|
||||
// i2c_cmd_link_delete(cmd);
|
||||
}
|
||||
|
||||
//-----------------------------------------
|
||||
// void select_register(uint8_t device_address, uint8_t register_address)
|
||||
// {
|
||||
// i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
// i2c_master_start(cmd);
|
||||
// i2c_master_write_byte(cmd, (device_address << 1) | I2C_MASTER_WRITE, 1);
|
||||
// i2c_master_write_byte(cmd, register_address, 1);
|
||||
// i2c_master_stop(cmd);
|
||||
// i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);
|
||||
// i2c_cmd_link_delete(cmd);
|
||||
// }
|
||||
|
||||
// int8_t esp32_i2c_read_bytes(uint8_t device_address, uint8_t register_address, uint8_t size, uint8_t *data)
|
||||
// {
|
||||
// select_register(device_address, register_address);
|
||||
// i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
// i2c_master_start(cmd);
|
||||
// i2c_master_write_byte(cmd, (device_address << 1) | I2C_MASTER_READ, 1);
|
||||
|
||||
// if (size > 1)
|
||||
// i2c_master_read(cmd, data, size - 1, 0);
|
||||
|
||||
// i2c_master_read_byte(cmd, data + size - 1, 1);
|
||||
|
||||
// i2c_master_stop(cmd);
|
||||
// i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);
|
||||
// i2c_cmd_link_delete(cmd);
|
||||
|
||||
// return (size);
|
||||
// }
|
||||
|
||||
// int8_t esp32_i2c_read_byte(uint8_t device_address, uint8_t register_address, uint8_t *data)
|
||||
// {
|
||||
// return (esp32_i2c_read_bytes(device_address, register_address, 1, data));
|
||||
// }
|
||||
|
||||
// int8_t esp32_i2c_read_bits(uint8_t device_address, uint8_t register_address, uint8_t bit_start, uint8_t size, uint8_t *data)
|
||||
// {
|
||||
// uint8_t bit;
|
||||
// uint8_t count;
|
||||
|
||||
// if ((count = esp32_i2c_read_byte(device_address, register_address, &bit)))
|
||||
// {
|
||||
// uint8_t mask = ((1 << size) - 1) << (bit_start - size + 1);
|
||||
|
||||
// bit &= mask;
|
||||
// bit >>= (bit_start - size + 1);
|
||||
// *data = bit;
|
||||
// }
|
||||
|
||||
// return (count);
|
||||
// }
|
||||
|
||||
// int8_t esp32_i2c_read_bit(uint8_t device_address, uint8_t register_address, uint8_t bit_number, uint8_t *data)
|
||||
// {
|
||||
// uint8_t bit;
|
||||
// uint8_t count = esp32_i2c_read_byte(device_address, register_address, &bit);
|
||||
|
||||
// *data = bit & (1 << bit_number);
|
||||
|
||||
// return (count);
|
||||
// }
|
||||
|
||||
// bool esp32_i2c_write_bytes(uint8_t device_address, uint8_t register_address, uint8_t size, uint8_t *data)
|
||||
// {
|
||||
// i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
// i2c_master_start(cmd);
|
||||
// i2c_master_write_byte(cmd, (device_address << 1) | I2C_MASTER_WRITE, 1);
|
||||
// i2c_master_write_byte(cmd, register_address, 1);
|
||||
// i2c_master_write(cmd, data, size - 1, 0);
|
||||
// i2c_master_write_byte(cmd, data[size - 1], 1);
|
||||
// i2c_master_stop(cmd);
|
||||
// i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);
|
||||
// i2c_cmd_link_delete(cmd);
|
||||
|
||||
// return (true);
|
||||
// }
|
||||
|
||||
// bool esp32_i2c_write_byte(uint8_t device_address, uint8_t register_address, uint8_t data)
|
||||
// {
|
||||
// i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
// i2c_master_start(cmd);
|
||||
// i2c_master_write_byte(cmd, (device_address << 1) | I2C_MASTER_WRITE, 1);
|
||||
// i2c_master_write_byte(cmd, register_address, 1);
|
||||
// i2c_master_write_byte(cmd, data, 1);
|
||||
// i2c_master_stop(cmd);
|
||||
// i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);
|
||||
// i2c_cmd_link_delete(cmd);
|
||||
|
||||
// return (true);
|
||||
// }
|
||||
|
||||
// bool esp32_i2c_write_bits(uint8_t device_address, uint8_t register_address, uint8_t bit_start, uint8_t size, uint8_t data)
|
||||
// {
|
||||
// uint8_t bit = 0;
|
||||
|
||||
// if (esp32_i2c_read_byte(device_address, register_address, &bit) != 0)
|
||||
// {
|
||||
// uint8_t mask = ((1 << size) - 1) << (bit_start - size + 1);
|
||||
// data <<= (bit_start - size + 1);
|
||||
// data &= mask;
|
||||
// bit &= ~(mask);
|
||||
// bit |= data;
|
||||
// return (esp32_i2c_write_byte(device_address, register_address, bit));
|
||||
// }
|
||||
// else
|
||||
// return (false);
|
||||
// }
|
||||
|
||||
bool esp32_i2c_write_bit(uint8_t device_address, uint8_t register_address, uint8_t bit_number, uint8_t data)
|
||||
{
|
||||
uint8_t bit;
|
||||
|
||||
esp32_i2c_read_byte(device_address, register_address, &bit);
|
||||
|
||||
if (data != 0)
|
||||
bit = (bit | (1 << bit_number));
|
||||
else
|
||||
bit = (bit & ~(1 << bit_number));
|
||||
|
||||
return (esp32_i2c_write_byte(device_address, register_address, bit));
|
||||
}
|
||||
|
||||
int8_t esp32_i2c_write_word(uint8_t device_address, uint8_t register_address, uint8_t data)
|
||||
{
|
||||
uint8_t data_1[] = {(uint8_t)(data >> 8), (uint8_t)(data & 0xFF)};
|
||||
|
||||
esp32_i2c_write_bytes(device_address, register_address, 2, data_1);
|
||||
|
||||
return (1);
|
||||
}
|
||||
19
ESP32/main/H2201_i2c.h
Normal file
19
ESP32/main/H2201_i2c.h
Normal file
@@ -0,0 +1,19 @@
|
||||
#ifndef __H2201_I2C_H__
|
||||
#define __H2201_I2C_H__
|
||||
|
||||
//#include "driver/i2c.h"
|
||||
|
||||
#define H2201_I2C_TAG "H2201_I2C"
|
||||
|
||||
#define I2C_MASTER_SCL_IO 22 /*!< gpio number for I2C master clock */
|
||||
#define I2C_MASTER_SDA_IO 21 /*!< gpio number for I2C master data */
|
||||
#define I2C_MASTER_NUM 0 /*!< I2C port number for master dev */
|
||||
#define I2C_MASTER_FREQ_HZ 500000 /*!< I2C master clock frequency */
|
||||
|
||||
#define I2C_MASTER_TX_BUF_DISABLE 0 /*!< I2C master doesn't need buffer */
|
||||
#define I2C_MASTER_RX_BUF_DISABLE 0 /*!< I2C master doesn't need buffer */
|
||||
|
||||
void H2201_i2c_master_init(void);
|
||||
void H2201_i2c_adau1761_init(void);
|
||||
|
||||
#endif /* __H2201_I2C_H__ */
|
||||
143
ESP32/main/SigmaStudioFW.h
Normal file
143
ESP32/main/SigmaStudioFW.h
Normal file
@@ -0,0 +1,143 @@
|
||||
/*
|
||||
* File: SigmaStudioFW.h
|
||||
*
|
||||
* Description: SigmaStudio System Framwork macro definitions. These
|
||||
* macros should be implemented for your system's software.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright <20> 2008 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __SIGMASTUDIOFW_H__
|
||||
#define __SIGMASTUDIOFW_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <inttypes.h>
|
||||
|
||||
/*
|
||||
* TODO: Update for your system's data type
|
||||
*/
|
||||
typedef unsigned short ADI_DATA_U16;
|
||||
typedef unsigned char ADI_REG_TYPE;
|
||||
|
||||
#define Address_Length 2
|
||||
void SIGMA_WRITE_REGISTER_BLOCK(uint8_t devAddress, uint16_t address, int length, ADI_REG_TYPE *pData);
|
||||
void SIGMA_WRITE_DELAY(int devAddress, int length, ADI_REG_TYPE *pData);
|
||||
|
||||
/*
|
||||
* Parameter data format
|
||||
*/
|
||||
#define SIGMASTUDIOTYPE_FIXPOINT 0
|
||||
#define SIGMASTUDIOTYPE_INTEGER 1
|
||||
|
||||
/*
|
||||
* Write to a single Device register
|
||||
*/
|
||||
#define SIGMA_WRITE_REGISTER(devAddress, address, dataLength, data) \
|
||||
{ /*TODO: implement macro or define as function*/ \
|
||||
}
|
||||
|
||||
/*
|
||||
* TODO: CUSTOM MACRO IMPLEMENTATION
|
||||
* Write to multiple Device registers
|
||||
*/
|
||||
void SIGMA_WRITE_REGISTER_BLOCK(uint8_t devAddress, uint16_t address, int length, ADI_REG_TYPE *pData)
|
||||
{
|
||||
// SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R0_SAMPLE_RATE_SETTING_IC1_Default);
|
||||
// 0x70 0x40EB 1 0x7F
|
||||
|
||||
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
i2c_master_start(cmd);
|
||||
i2c_master_write_byte(cmd, devAddress, true); // write address 0x70
|
||||
i2c_master_write_byte(cmd, (address >> 8), true);
|
||||
i2c_master_write_byte(cmd, (address & 0xFF), true);
|
||||
i2c_master_write(cmd, pData, length, true);
|
||||
i2c_master_stop(cmd);
|
||||
esp_err_t err = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 10 / portTICK_PERIOD_MS);
|
||||
if (err == ESP_OK)
|
||||
{
|
||||
ESP_LOGI(H2201_I2C_TAG, "ADAU1761 block write successfully");
|
||||
}
|
||||
else
|
||||
{
|
||||
ESP_LOGE(H2201_I2C_TAG, "ADAU1761 block write failed. code: 0x%.2X", err);
|
||||
}
|
||||
|
||||
i2c_cmd_link_delete(cmd);
|
||||
}
|
||||
|
||||
void SIGMA_WRITE_DELAY(int devAddress, int length, ADI_REG_TYPE *pData)
|
||||
{
|
||||
// int cnt=0;
|
||||
int nCount = 0;
|
||||
// int data_length = length - Address_Length;
|
||||
// ADI_REG_TYPE data[4]={0x05, 0xF5, 0xE1, 0x00};
|
||||
// for(cnt=0; cnt<data_length; cnt++)
|
||||
// {
|
||||
// nCount &= pData[cnt] >> (8*cnt);
|
||||
// }
|
||||
// for(cnt=0; cnt<4; cnt++)
|
||||
// {
|
||||
// nCount += data[cnt];
|
||||
// nCount = nCount<<(8);
|
||||
//
|
||||
// }
|
||||
// nCount=0xFFFFFF;
|
||||
// nCount=0x15752A00; //5 secs approx
|
||||
// nCount=0x05F5E100; //5 secs approx
|
||||
nCount = 0xFFFFF;
|
||||
for (; nCount != 0; nCount--)
|
||||
;
|
||||
}
|
||||
|
||||
/*
|
||||
* Read device registers
|
||||
*/
|
||||
#define SIGMA_READ_REGISTER(devAddress, address, length, pData) \
|
||||
{ /*TODO: implement macro or define as function*/ \
|
||||
}
|
||||
|
||||
/*
|
||||
* Set a register field's value
|
||||
*/
|
||||
#define SIGMA_SET_REGSITER_FIELD(regVal, fieldVal, fieldMask, fieldShift) \
|
||||
{ \
|
||||
(regVal) = (((regVal) & (~(fieldMask))) | (((fieldVal) << (fieldShift)) && (fieldMask))) \
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the value of a register field
|
||||
*/
|
||||
#define SIGMA_GET_REGSITER_FIELD(regVal, fieldMask, fieldShift) \
|
||||
{ \
|
||||
((regVal) & (fieldMask)) >> (fieldShift) \
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert a floating-point value to SigmaDSP (5.23) fixed point format
|
||||
* This optional macro is intended for systems having special implementation
|
||||
* requirements (for example: limited memory size or endianness)
|
||||
*/
|
||||
#define SIGMASTUDIOTYPE_FIXPOINT_CONVERT(_value) \
|
||||
{ /*TODO: IMPLEMENT MACRO*/ \
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert integer data to system compatible format
|
||||
* This optional macro is intended for systems having special implementation
|
||||
* requirements (for example: limited memory size or endianness)
|
||||
*/
|
||||
#define SIGMASTUDIOTYPE_INTEGER_CONVERT(_value) \
|
||||
{ /*TODO: IMPLEMENT MACRO*/ \
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -7,8 +7,6 @@
|
||||
#include "freertos/queue.h"
|
||||
#include "freertos/task.h"
|
||||
#include "esp_log.h"
|
||||
//#include "driver/i2s.h"
|
||||
//#include "freertos/ringbuf.h"
|
||||
|
||||
#include "H2201_app.h"
|
||||
|
||||
|
||||
@@ -30,11 +30,14 @@
|
||||
#include "esp_a2dp_api.h"
|
||||
#include "esp_avrc_api.h"
|
||||
#include "driver/i2s.h"
|
||||
#include "driver/i2c.h"
|
||||
|
||||
#include "H2201_i2c.h"
|
||||
#include "H2201_app.h"
|
||||
#include "H2201_avrcp.h"
|
||||
#include "H2201_a2dp.h"
|
||||
|
||||
#define H2201_MAIN_TAG "H2201_MAIN"
|
||||
|
||||
/* event for handler "bt_av_hdl_stack_up */
|
||||
enum
|
||||
@@ -58,6 +61,9 @@ void app_main(void)
|
||||
}
|
||||
ESP_ERROR_CHECK(err);
|
||||
|
||||
H2201_i2c_master_init();
|
||||
H2201_i2c_adau1761_init();
|
||||
|
||||
i2s_config_t i2s_config = {
|
||||
.mode = I2S_MODE_MASTER | I2S_MODE_TX, // Only TX
|
||||
.sample_rate = 48000,
|
||||
|
||||
@@ -960,14 +960,13 @@ CONFIG_HEAP_TRACING_OFF=y
|
||||
# CONFIG_LOG_DEFAULT_LEVEL_NONE is not set
|
||||
# CONFIG_LOG_DEFAULT_LEVEL_ERROR is not set
|
||||
# CONFIG_LOG_DEFAULT_LEVEL_WARN is not set
|
||||
CONFIG_LOG_DEFAULT_LEVEL_INFO=y
|
||||
# CONFIG_LOG_DEFAULT_LEVEL_DEBUG is not set
|
||||
# CONFIG_LOG_DEFAULT_LEVEL_INFO is not set
|
||||
CONFIG_LOG_DEFAULT_LEVEL_DEBUG=y
|
||||
# CONFIG_LOG_DEFAULT_LEVEL_VERBOSE is not set
|
||||
CONFIG_LOG_DEFAULT_LEVEL=3
|
||||
CONFIG_LOG_DEFAULT_LEVEL=4
|
||||
CONFIG_LOG_MAXIMUM_EQUALS_DEFAULT=y
|
||||
# CONFIG_LOG_MAXIMUM_LEVEL_DEBUG is not set
|
||||
# CONFIG_LOG_MAXIMUM_LEVEL_VERBOSE is not set
|
||||
CONFIG_LOG_MAXIMUM_LEVEL=3
|
||||
CONFIG_LOG_MAXIMUM_LEVEL=4
|
||||
CONFIG_LOG_COLORS=y
|
||||
CONFIG_LOG_TIMESTAMP_SOURCE_RTOS=y
|
||||
# CONFIG_LOG_TIMESTAMP_SOURCE_SYSTEM is not set
|
||||
|
||||
Reference in New Issue
Block a user