SAM9X60 has another bit as slow clock selector (OSCSEL).
Fix the defines accordingly.
SAM9X60 does not have a bit to disable the internal RC slow clock (it is
always enabled).
Thus the function for this feature should not be available.
Reported-by: Ilie Galan <ilie.galan@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Datasheet recommends different values for UPLL and PLLA analog control
register.
Adapt accordingly.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
at91_sdhc_hw_init checks whether the over-consumption erratum fix is in
place by evaluating the SDMMC_CALCR register. However, the check is a
bitwise OR, which results in the condition always being true. Use a
bitwise AND to check if the ALWYSON bit is set.
Signed-off-by: Florian Larysch <florian.larysch@grandcentrix.net>
On some boards, the QSPI is not booting correctly in MODE0
MODE3 is the correct operating mode.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
This bit should not be selected for SDRAMC controller.
It is only for DDR memories.
Fixes: 7c62e974cc ("board: sam9x60_sdr_sip_eb: introduce SAM9X60 SDR SIP Engineering board")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
as per K&R etc. memcpy should return a pointer to destination not
destination + size.
This makes GCC 8.2.0+ get confused when using at91bootstrap memcpy
instead of it's own lib's memcpy implementation
Signed-off-by: Christian Hack <christian.hack@ams-it.com.au>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
The field named ICP_PLLA[1:0] must be written to 0.
Even if its default value is 0, it is wrongly re-written to 0x3 by the ROMCode.
We must correct this before that the DDR initialization sequence is started.
Tested-by: Marco Cardellini <marco.cardellini@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Commit 1965938c10 introduced pmc-v1.h header. In v2 of the patch series
that was send internally the content of pmc-v1.h was preserved from what
was defined in v1 of the patch series (internally) related to SAMA5D2.
But the pmc-v1.h introduced by commit 1965938c10 should have been
preserved the content of what was in include/arch/at91_pmc/pmc.h.
Fixes: 1965938c10 ("include: arch: at91_pmc: introduce a new header for 1st PMC version")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
#ifdef PMC_PLLICPR is not needed anymore since the driver is selected
only by SoCs that supports it.
Fixes: 144f474721 ("driver: pmc: move pll code into its own file")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
B/w v1 and v2 of internal patches the usage of *_ALT_* related macros
was restored but not for PLLA register. Revert it also for PLLA register.
Fixes: 144f474721 ("driver: pmc: move pll code into its own file")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
If we boot from nandflash, DDR will not work unless we specifically
configure nand lines to the real D16-D31 where it's connected.
RomCode will disable this bit if NAND is used.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add support and defconfig for booting from QSPI memory which
is available on the WLSOM cpu module on QSPI1 controller
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Add all timer values for MPDDRC_LPDDR2_LPDDR3_DDR3_CAL_MR4 register
on the LPDDR2 for the SiP.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Add support for the SAMA5D27-WLSOM1-EK. It's based on the Microchip WireLess
SoM which contains the SAMA5D27 LPDDR2 2Gbits SiP.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Add the MR4 Read bit field in MPDDRC_LPDDR2_LPDDR3_DDR3_CAL_MR4 register
macro for writing this value.
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
The QSPI controller has 2 clocks, both mandatory: the qspi
peripheral clock and the qspi system clock. Add the qspi system
clock.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
The inactive state value of QSCK is logic level zero
Data is captured on the leading edge of QSCK and changed
on the following edge of QSCK.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
It has dedicated registers to specify a read or a write instruction:
Read Instruction Code Register (RICR) and Write Instruction Code
Register (WICR). ICR/RICR/WICR have identical fields.
Even if the controller defines a dedicated bit for APB Transfer Type
(APBTFRTYP), there is no need to use it, since the driver now works only
with AHB transfers.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
[eugen.hristev@microchip.com]: converted this feature as Kconfig
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
qspi could loop forever when the expected interupts are not
raised. Break the loop with a timeout.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
- EBI Chip Select Register is now in SFR,
- the pins are set to default values,
- timings are matching MT29F4G08BABWP's nand flash requirements.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Enable flexcom support and TWI for flexcom0.
On this bus there is an EEPROM with board information
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
