Added button with beep
This commit is contained in:
Martijn Scheepers
Binary file not shown.
@@ -6,9 +6,34 @@ dataLoad3_SafeLoad 4
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dataLoadEnd_SafeLoad 5
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addressLoad_SafeLoad 6
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numLoad_SafeLoad 7
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NxNMixer1940Alg1_00_00_1 8
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NxNMixer1940Alg1_00_01_1 9
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NxNMixer1940Alg2_00_00_2 10
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NxNMixer1940Alg2_00_01_2 11
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Gain1940AlgNS1_3 12
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Gain1940AlgNS2_4 13
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SwitchAlg1ison_1 8
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Optimized2ChimeAlgWGainGUI1numberofpoints 9
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Optimized2ChimeAlgWGainGUI1table 10
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Optimized2ChimeAlgWGainGUI1table_autoincremented 11
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Optimized2ChimeAlgWGainGUI1table_autoincremented 12
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Optimized2ChimeAlgWGainGUI1table_autoincremented 13
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Optimized2ChimeAlgWGainGUI1numberofgainpoints 14
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Optimized2ChimeAlgWGainGUI1gaintable 15
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Optimized2ChimeAlgWGainGUI1gaintable_autoincremented 16
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Optimized2ChimeAlgWGainGUI1gaintable_autoincremented 17
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Optimized2ChimeAlgWGainGUI1freqincrement 18
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Optimized2ChimeAlgWGainGUI1freqincrement_autoincremented 19
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Optimized2ChimeAlgWGainGUI1freqincrement_autoincremented 20
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Optimized2ChimeAlgWGainGUI1freqincrement_autoincremented 21
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Optimized2ChimeAlgWGainGUI1startfreq 22
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Optimized2ChimeAlgWGainGUI1lowestfreq 23
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Optimized2ChimeAlgWGainGUI1gainincrementtable 24
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Optimized2ChimeAlgWGainGUI1gainincrementtable_autoincremented 25
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Optimized2ChimeAlgWGainGUI1gainincrementtable_autoincremented 26
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Optimized2ChimeAlgWGainGUI1startgain 27
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Optimized2ChimeAlgWGainGUI1lowestgain 28
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Optimized2ChimeAlgWGainGUI1mask 29
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SingleCtrlSplit1_3 30
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NxNMixer1940Alg1_00_00_4 31
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NxNMixer1940Alg1_00_01_4 32
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NxNMixer1940Alg1_00_02_4 33
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NxNMixer1940Alg2_00_00_5 34
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NxNMixer1940Alg2_00_01_5 35
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NxNMixer1940Alg2_00_02_5 36
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Gain1940AlgNS1_6 37
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Gain1940AlgNS2_7 38
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@@ -7,32 +7,35 @@ Build date = 12/23/2020 at 4:27 AM
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(Note: Estimates are based on a 48 kHz sample rate)
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Instructions used:
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63 (out of a possible 1024 )
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167 (out of a possible 1024 )
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Modulo Data RAM used (X Memory):
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8 (out of a possible 4096 )
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32 (out of a possible 4096 )
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Non Modulo Data RAM used (X Memory):
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0 (out of a possible 4096 )
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Parameter RAM used (Y Memory):
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14 (out of a possible 1024 )
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39 (out of a possible 1024 )
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Instance Mips Inst Data Coeff Other
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(max)
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Beep 96 96 21 21
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Beginning 19 19 0 1
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SafeLoadCode 15 15 0 7
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Input1 8 8 4 0
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End 5 5 0 0
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Right Mixer 3 3 1 2
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Left Mixer 3 3 1 2
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Left Master 3 3 1 1
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Beep Splitter 4 4 2 1
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Right Mixer 4 4 1 3
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Left Mixer 4 4 1 3
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Right Master 3 3 1 1
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Left Master 3 3 1 1
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Beep Switch 2 2 1 1
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Output1 2 2 0 0
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Output2 2 2 0 0
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Subroutines called:
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----------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Total 63 63 8 14
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Total 167 167 32 39
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----------------------------------------------------------------------------------------------------------------------------------------------------------------------
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(%) 6% 6% 0% 1%
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(%) 16% 16% 1% 4%
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Files written:
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program_data.dat - load file for downloading code using ADI loader
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@@ -40,21 +40,125 @@
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0x00 , 0x10 , 0x00 , 0xE2 , 0x00 ,
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0xFD , 0x2D , 0x08 , 0x20 , 0x00 ,
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0x00 , 0x18 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x00 , 0x08 , 0x20 , 0x00 ,
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0x00 , 0x10 , 0x09 , 0x22 , 0x00 ,
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0xFF , 0xE8 , 0x08 , 0x20 , 0x00 ,
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0x00 , 0x20 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x08 , 0x0A , 0x20 , 0x00 ,
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0x00 , 0x18 , 0x0B , 0x22 , 0x00 ,
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0x00 , 0x28 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x28 , 0x0C , 0x20 , 0x00 ,
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0x00 , 0x30 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0x00 , 0x20 , 0x0D , 0x20 , 0x00 ,
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0xFF , 0xED , 0x1F , 0x20 , 0x00 ,
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0x00 , 0x35 , 0x08 , 0x22 , 0x00 ,
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0x00 , 0x38 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x25 , 0x08 , 0x20 , 0x08 ,
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0xFF , 0xF5 , 0x08 , 0x20 , 0x00 ,
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0x00 , 0x3D , 0x08 , 0x20 , 0x26 ,
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0x00 , 0x38 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x40 , 0x00 , 0xC0 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0x00 , 0x3D , 0x08 , 0x20 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0xFF , 0xE8 , 0x0A , 0x21 , 0x00 ,
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0x00 , 0x3D , 0x08 , 0x22 , 0x48 ,
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0x00 , 0x45 , 0x08 , 0x20 , 0x00 ,
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0xFF , 0xFD , 0x08 , 0x22 , 0x27 ,
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0x00 , 0x48 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x4D , 0x08 , 0x20 , 0x00 ,
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0xFF , 0xE8 , 0x09 , 0x22 , 0x48 ,
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0xFF , 0xE8 , 0x09 , 0x20 , 0x00 ,
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0x00 , 0x4D , 0x08 , 0x20 , 0x27 ,
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0x00 , 0x48 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x25 , 0x08 , 0x20 , 0x08 ,
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0xFF , 0xF5 , 0x08 , 0x20 , 0x00 ,
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0x00 , 0x4D , 0x08 , 0x20 , 0x26 ,
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0x00 , 0x48 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x3D , 0x08 , 0x20 , 0x08 ,
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0xFF , 0xE8 , 0x16 , 0x20 , 0x00 ,
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0x00 , 0x75 , 0x08 , 0x20 , 0x26 ,
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0x00 , 0x70 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x75 , 0x08 , 0x20 , 0x00 ,
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0xFF , 0xE8 , 0x17 , 0x22 , 0x48 ,
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0xFF , 0xE8 , 0x17 , 0x20 , 0x00 ,
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0x00 , 0x75 , 0x08 , 0x20 , 0x25 ,
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0x00 , 0x70 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x48 , 0x00 , 0xC0 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0x00 , 0x60 , 0x12 , 0x21 , 0x00 ,
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0x00 , 0x70 , 0x12 , 0x35 , 0x00 ,
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0x00 , 0x78 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0x00 , 0x68 , 0x00 , 0xF2 , 0x00 ,
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0x00 , 0x50 , 0x00 , 0xC0 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0xFF , 0xE8 , 0x0F , 0x21 , 0x00 ,
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0x00 , 0x3D , 0x08 , 0x22 , 0x48 ,
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0x00 , 0x55 , 0x08 , 0x20 , 0x00 ,
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0xFF , 0xFD , 0x08 , 0x22 , 0x27 ,
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0x00 , 0x58 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x5D , 0x08 , 0x20 , 0x00 ,
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0xFF , 0xE8 , 0x0E , 0x22 , 0x48 ,
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0xFF , 0xE8 , 0x0E , 0x20 , 0x00 ,
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||||
0x00 , 0x5D , 0x08 , 0x20 , 0x27 ,
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0x00 , 0x58 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x25 , 0x08 , 0x20 , 0x08 ,
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0xFF , 0xF5 , 0x08 , 0x20 , 0x00 ,
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0x00 , 0x5D , 0x08 , 0x20 , 0x26 ,
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0x00 , 0x58 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x3D , 0x08 , 0x20 , 0x08 ,
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0xFF , 0xE8 , 0x1B , 0x20 , 0x00 ,
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0x00 , 0x95 , 0x08 , 0x20 , 0x26 ,
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0x00 , 0x90 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x95 , 0x08 , 0x20 , 0x00 ,
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0xFF , 0xE8 , 0x1C , 0x22 , 0x48 ,
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0xFF , 0xE8 , 0x1C , 0x20 , 0x00 ,
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0x00 , 0x95 , 0x08 , 0x20 , 0x25 ,
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0x00 , 0x90 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x58 , 0x00 , 0xC0 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0x00 , 0x80 , 0x18 , 0x21 , 0x00 ,
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0x00 , 0x90 , 0x18 , 0x35 , 0x00 ,
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0x00 , 0x98 , 0x00 , 0xE2 , 0x00 ,
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0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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0x00 , 0x88 , 0x00 , 0xF2 , 0x00 ,
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||||
0x00 , 0xB5 , 0x1F , 0x20 , 0x00 ,
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||||
0x00 , 0xA5 , 0x08 , 0x22 , 0x00 ,
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||||
0x00 , 0x7D , 0x18 , 0x22 , 0x00 ,
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||||
0x00 , 0x00 , 0x1D , 0xA0 , 0x00 ,
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||||
0x00 , 0xA8 , 0x00 , 0xEA , 0x00 ,
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||||
0x00 , 0xB8 , 0x00 , 0xF2 , 0x00 ,
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||||
0x00 , 0xA8 , 0x00 , 0xC0 , 0x00 ,
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||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
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||||
0x00 , 0x04 , 0x01 , 0xA1 , 0x00 ,
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||||
0xFF , 0xE5 , 0x08 , 0x20 , 0x00 ,
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||||
0x00 , 0x04 , 0x00 , 0xA1 , 0x00 ,
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||||
0xFF , 0xE5 , 0x08 , 0x22 , 0x40 ,
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||||
0x00 , 0xC0 , 0x00 , 0xE2 , 0x00 ,
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||||
0x00 , 0xB8 , 0x00 , 0xC0 , 0x00 ,
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||||
0x00 , 0xC7 , 0xFF , 0x20 , 0x00 ,
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||||
0xFF , 0xE5 , 0x08 , 0x22 , 0x00 ,
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||||
0x00 , 0xC8 , 0x00 , 0xE2 , 0x00 ,
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||||
0x00 , 0xC8 , 0x00 , 0xC0 , 0x00 ,
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||||
0x00 , 0x9F , 0xFF , 0x20 , 0x00 ,
|
||||
0x00 , 0x28 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x28 , 0x1E , 0x20 , 0x00 ,
|
||||
0x00 , 0xD0 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x28 , 0x1E , 0x20 , 0x00 ,
|
||||
0x00 , 0xD8 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x00 , 0x1F , 0x20 , 0x00 ,
|
||||
0x00 , 0x10 , 0x20 , 0x22 , 0x00 ,
|
||||
0x00 , 0xD0 , 0x21 , 0x22 , 0x00 ,
|
||||
0x00 , 0xE0 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x08 , 0x22 , 0x20 , 0x00 ,
|
||||
0x00 , 0x18 , 0x23 , 0x22 , 0x00 ,
|
||||
0x00 , 0xD8 , 0x24 , 0x22 , 0x00 ,
|
||||
0x00 , 0xE8 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0xE8 , 0x25 , 0x20 , 0x00 ,
|
||||
0x00 , 0xF0 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0xE0 , 0x26 , 0x20 , 0x00 ,
|
||||
0x00 , 0xF8 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0xFD , 0x08 , 0x20 , 0x00 ,
|
||||
0xFD , 0xB0 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x35 , 0x08 , 0x20 , 0x00 ,
|
||||
0x00 , 0xF5 , 0x08 , 0x20 , 0x00 ,
|
||||
0xFD , 0xB8 , 0x00 , 0xE2 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0xFE , 0x30 , 0x00 , 0x00 , 0x00 ,
|
||||
|
||||
@@ -40,21 +40,125 @@ FD25082000
|
||||
001000E200
|
||||
FD2D082000
|
||||
001800E200
|
||||
0000082000
|
||||
0010092200
|
||||
FFE8082000
|
||||
002000E200
|
||||
00080A2000
|
||||
00180B2200
|
||||
002800E200
|
||||
00280C2000
|
||||
003000E200
|
||||
0000000000
|
||||
00200D2000
|
||||
FFED1F2000
|
||||
0035082200
|
||||
003800E200
|
||||
0025082008
|
||||
FFF5082000
|
||||
003D082026
|
||||
003800E200
|
||||
004000C000
|
||||
0000000000
|
||||
003D082000
|
||||
0000000000
|
||||
FFE80A2100
|
||||
003D082248
|
||||
0045082000
|
||||
FFFD082227
|
||||
004800E200
|
||||
004D082000
|
||||
FFE8092248
|
||||
FFE8092000
|
||||
004D082027
|
||||
004800E200
|
||||
0025082008
|
||||
FFF5082000
|
||||
004D082026
|
||||
004800E200
|
||||
003D082008
|
||||
FFE8162000
|
||||
0075082026
|
||||
007000E200
|
||||
0075082000
|
||||
FFE8172248
|
||||
FFE8172000
|
||||
0075082025
|
||||
007000E200
|
||||
004800C000
|
||||
0000000000
|
||||
0000000000
|
||||
0060122100
|
||||
0070123500
|
||||
007800E200
|
||||
0000000000
|
||||
006800F200
|
||||
005000C000
|
||||
0000000000
|
||||
0000000000
|
||||
FFE80F2100
|
||||
003D082248
|
||||
0055082000
|
||||
FFFD082227
|
||||
005800E200
|
||||
005D082000
|
||||
FFE80E2248
|
||||
FFE80E2000
|
||||
005D082027
|
||||
005800E200
|
||||
0025082008
|
||||
FFF5082000
|
||||
005D082026
|
||||
005800E200
|
||||
003D082008
|
||||
FFE81B2000
|
||||
0095082026
|
||||
009000E200
|
||||
0095082000
|
||||
FFE81C2248
|
||||
FFE81C2000
|
||||
0095082025
|
||||
009000E200
|
||||
005800C000
|
||||
0000000000
|
||||
0000000000
|
||||
0080182100
|
||||
0090183500
|
||||
009800E200
|
||||
0000000000
|
||||
008800F200
|
||||
00B51F2000
|
||||
00A5082200
|
||||
007D182200
|
||||
00001DA000
|
||||
00A800EA00
|
||||
00B800F200
|
||||
00A800C000
|
||||
0000000000
|
||||
0000000000
|
||||
000401A100
|
||||
FFE5082000
|
||||
000400A100
|
||||
FFE5082240
|
||||
00C000E200
|
||||
00B800C000
|
||||
00C7FF2000
|
||||
FFE5082200
|
||||
00C800E200
|
||||
00C800C000
|
||||
009FFF2000
|
||||
002800E200
|
||||
00281E2000
|
||||
00D000E200
|
||||
00281E2000
|
||||
00D800E200
|
||||
00001F2000
|
||||
0010202200
|
||||
00D0212200
|
||||
00E000E200
|
||||
0008222000
|
||||
0018232200
|
||||
00D8242200
|
||||
00E800E200
|
||||
00E8252000
|
||||
00F000E200
|
||||
0000000000
|
||||
00E0262000
|
||||
00F800E200
|
||||
0000000000
|
||||
00FD082000
|
||||
FDB000E200
|
||||
0035082000
|
||||
00F5082000
|
||||
FDB800E200
|
||||
0000000000
|
||||
FE30000000
|
||||
|
||||
@@ -40,21 +40,125 @@
|
||||
0000000000010000000000001110001000000000
|
||||
1111110100101101000010000010000000000000
|
||||
0000000000011000000000001110001000000000
|
||||
0000000000000000000010000010000000000000
|
||||
0000000000010000000010010010001000000000
|
||||
1111111111101000000010000010000000000000
|
||||
0000000000100000000000001110001000000000
|
||||
0000000000001000000010100010000000000000
|
||||
0000000000011000000010110010001000000000
|
||||
0000000000101000000000001110001000000000
|
||||
0000000000101000000011000010000000000000
|
||||
0000000000110000000000001110001000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000100000000011010010000000000000
|
||||
1111111111101101000111110010000000000000
|
||||
0000000000110101000010000010001000000000
|
||||
0000000000111000000000001110001000000000
|
||||
0000000000100101000010000010000000001000
|
||||
1111111111110101000010000010000000000000
|
||||
0000000000111101000010000010000000100110
|
||||
0000000000111000000000001110001000000000
|
||||
0000000001000000000000001100000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000111101000010000010000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
1111111111101000000010100010000100000000
|
||||
0000000000111101000010000010001001001000
|
||||
0000000001000101000010000010000000000000
|
||||
1111111111111101000010000010001000100111
|
||||
0000000001001000000000001110001000000000
|
||||
0000000001001101000010000010000000000000
|
||||
1111111111101000000010010010001001001000
|
||||
1111111111101000000010010010000000000000
|
||||
0000000001001101000010000010000000100111
|
||||
0000000001001000000000001110001000000000
|
||||
0000000000100101000010000010000000001000
|
||||
1111111111110101000010000010000000000000
|
||||
0000000001001101000010000010000000100110
|
||||
0000000001001000000000001110001000000000
|
||||
0000000000111101000010000010000000001000
|
||||
1111111111101000000101100010000000000000
|
||||
0000000001110101000010000010000000100110
|
||||
0000000001110000000000001110001000000000
|
||||
0000000001110101000010000010000000000000
|
||||
1111111111101000000101110010001001001000
|
||||
1111111111101000000101110010000000000000
|
||||
0000000001110101000010000010000000100101
|
||||
0000000001110000000000001110001000000000
|
||||
0000000001001000000000001100000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000001100000000100100010000100000000
|
||||
0000000001110000000100100011010100000000
|
||||
0000000001111000000000001110001000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000001101000000000001111001000000000
|
||||
0000000001010000000000001100000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
1111111111101000000011110010000100000000
|
||||
0000000000111101000010000010001001001000
|
||||
0000000001010101000010000010000000000000
|
||||
1111111111111101000010000010001000100111
|
||||
0000000001011000000000001110001000000000
|
||||
0000000001011101000010000010000000000000
|
||||
1111111111101000000011100010001001001000
|
||||
1111111111101000000011100010000000000000
|
||||
0000000001011101000010000010000000100111
|
||||
0000000001011000000000001110001000000000
|
||||
0000000000100101000010000010000000001000
|
||||
1111111111110101000010000010000000000000
|
||||
0000000001011101000010000010000000100110
|
||||
0000000001011000000000001110001000000000
|
||||
0000000000111101000010000010000000001000
|
||||
1111111111101000000110110010000000000000
|
||||
0000000010010101000010000010000000100110
|
||||
0000000010010000000000001110001000000000
|
||||
0000000010010101000010000010000000000000
|
||||
1111111111101000000111000010001001001000
|
||||
1111111111101000000111000010000000000000
|
||||
0000000010010101000010000010000000100101
|
||||
0000000010010000000000001110001000000000
|
||||
0000000001011000000000001100000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000010000000000110000010000100000000
|
||||
0000000010010000000110000011010100000000
|
||||
0000000010011000000000001110001000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000010001000000000001111001000000000
|
||||
0000000010110101000111110010000000000000
|
||||
0000000010100101000010000010001000000000
|
||||
0000000001111101000110000010001000000000
|
||||
0000000000000000000111011010000000000000
|
||||
0000000010101000000000001110101000000000
|
||||
0000000010111000000000001111001000000000
|
||||
0000000010101000000000001100000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000000000100000000011010000100000000
|
||||
1111111111100101000010000010000000000000
|
||||
0000000000000100000000001010000100000000
|
||||
1111111111100101000010000010001001000000
|
||||
0000000011000000000000001110001000000000
|
||||
0000000010111000000000001100000000000000
|
||||
0000000011000111111111110010000000000000
|
||||
1111111111100101000010000010001000000000
|
||||
0000000011001000000000001110001000000000
|
||||
0000000011001000000000001100000000000000
|
||||
0000000010011111111111110010000000000000
|
||||
0000000000101000000000001110001000000000
|
||||
0000000000101000000111100010000000000000
|
||||
0000000011010000000000001110001000000000
|
||||
0000000000101000000111100010000000000000
|
||||
0000000011011000000000001110001000000000
|
||||
0000000000000000000111110010000000000000
|
||||
0000000000010000001000000010001000000000
|
||||
0000000011010000001000010010001000000000
|
||||
0000000011100000000000001110001000000000
|
||||
0000000000001000001000100010000000000000
|
||||
0000000000011000001000110010001000000000
|
||||
0000000011011000001001000010001000000000
|
||||
0000000011101000000000001110001000000000
|
||||
0000000011101000001001010010000000000000
|
||||
0000000011110000000000001110001000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000011100000001001100010000000000000
|
||||
0000000011111000000000001110001000000000
|
||||
0000000000000000000000000000000000000000
|
||||
0000000011111101000010000010000000000000
|
||||
1111110110110000000000001110001000000000
|
||||
0000000000110101000010000010000000000000
|
||||
0000000011110101000010000010000000000000
|
||||
1111110110111000000000001110001000000000
|
||||
0000000000000000000000000000000000000000
|
||||
1111111000110000000000000000000000000000
|
||||
|
||||
@@ -1 +1 @@
|
||||
OPCODE_COUNT,Program_Count,62
|
||||
OPCODE_COUNT,Program_Count,166
|
||||
|
||||
@@ -7,6 +7,31 @@
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x03 ,
|
||||
0x00 , 0x00 , 0x03 , 0x90 ,
|
||||
0x00 , 0x00 , 0x3B , 0x40 ,
|
||||
0x00 , 0x00 , 0x4B , 0x00 ,
|
||||
0x00 , 0x00 , 0x4B , 0x60 ,
|
||||
0x00 , 0x00 , 0x00 , 0x02 ,
|
||||
0x00 , 0x00 , 0x03 , 0x90 ,
|
||||
0x00 , 0x00 , 0x4B , 0x00 ,
|
||||
0x00 , 0x00 , 0x4B , 0x60 ,
|
||||
0x00 , 0x80 , 0x8C , 0xDC ,
|
||||
0x00 , 0x80 , 0x00 , 0x3D ,
|
||||
0x00 , 0x7F , 0xDF , 0x60 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x1B , 0x4F ,
|
||||
0x00 , 0x00 , 0x1B , 0x4F ,
|
||||
0x00 , 0x81 , 0xA4 , 0x78 ,
|
||||
0x00 , 0x7F , 0xE7 , 0x0D ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x54 ,
|
||||
0x00 , 0x00 , 0x00 , 0x01 ,
|
||||
0x00 , 0x00 , 0x00 , 0xFF ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
Cell Name = Right Master
|
||||
Parameter Name = Gain1940AlgNS1
|
||||
Parameter Address = 12
|
||||
Parameter Address = 37
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
@@ -9,7 +9,7 @@ Parameter Data :
|
||||
|
||||
Cell Name = Left Master
|
||||
Parameter Name = Gain1940AlgNS2
|
||||
Parameter Address = 13
|
||||
Parameter Address = 38
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
@@ -18,7 +18,7 @@ Parameter Data :
|
||||
|
||||
Cell Name = Left Mixer
|
||||
Parameter Name = NxNMixer1940Alg1_00_00
|
||||
Parameter Address = 8
|
||||
Parameter Address = 31
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
@@ -27,7 +27,16 @@ Parameter Data :
|
||||
|
||||
Cell Name = Left Mixer
|
||||
Parameter Name = NxNMixer1940Alg1_00_01
|
||||
Parameter Address = 9
|
||||
Parameter Address = 32
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
|
||||
|
||||
|
||||
Cell Name = Left Mixer
|
||||
Parameter Name = NxNMixer1940Alg1_00_02
|
||||
Parameter Address = 33
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
@@ -36,7 +45,7 @@ Parameter Data :
|
||||
|
||||
Cell Name = Right Mixer
|
||||
Parameter Name = NxNMixer1940Alg2_00_00
|
||||
Parameter Address = 10
|
||||
Parameter Address = 34
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
@@ -45,13 +54,145 @@ Parameter Data :
|
||||
|
||||
Cell Name = Right Mixer
|
||||
Parameter Name = NxNMixer1940Alg2_00_01
|
||||
Parameter Address = 11
|
||||
Parameter Address = 35
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
|
||||
|
||||
|
||||
Cell Name = Right Mixer
|
||||
Parameter Name = NxNMixer1940Alg2_00_02
|
||||
Parameter Address = 36
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
|
||||
|
||||
|
||||
Cell Name = S Splitter1
|
||||
Parameter Name = SingleCtrlSplit1
|
||||
Parameter Address = 30
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
|
||||
|
||||
|
||||
Cell Name = Switch1
|
||||
Parameter Name = SwitchAlg1ison
|
||||
Parameter Address = 8
|
||||
Parameter Value = 1
|
||||
Parameter Data :
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1numberofpoints
|
||||
Parameter Address = 9
|
||||
Parameter Value = 3
|
||||
Parameter Data :
|
||||
0x00, 0x00, 0x00, 0x03,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1numberofgainpoints
|
||||
Parameter Address = 14
|
||||
Parameter Value = 2
|
||||
Parameter Data :
|
||||
0x00, 0x00, 0x00, 0x02,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1table
|
||||
Parameter Address = 10
|
||||
Parameter Data :
|
||||
0x00, 0x00, 0x03, 0x90,
|
||||
0x00, 0x00, 0x3B, 0x40,
|
||||
0x00, 0x00, 0x4B, 0x00,
|
||||
0x00, 0x00, 0x4B, 0x60,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1freqincrement
|
||||
Parameter Address = 18
|
||||
Parameter Data :
|
||||
0x00, 0x80, 0x8C, 0xDC,
|
||||
0x00, 0x80, 0x00, 0x3D,
|
||||
0x00, 0x7F, 0xDF, 0x60,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1startfreq
|
||||
Parameter Address = 22
|
||||
Parameter Value = 0.000833392143249512
|
||||
Parameter Data :
|
||||
0x00, 0x00, 0x1B, 0x4F,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1lowestfreq
|
||||
Parameter Address = 23
|
||||
Parameter Value = 0.000833392143249512
|
||||
Parameter Data :
|
||||
0x00, 0x00, 0x1B, 0x4F,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1gainincrementtable
|
||||
Parameter Address = 24
|
||||
Parameter Data :
|
||||
0x00, 0x81, 0xA4, 0x78,
|
||||
0x00, 0x7F, 0xE7, 0x0D,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1gaintable
|
||||
Parameter Address = 15
|
||||
Parameter Data :
|
||||
0x00, 0x00, 0x03, 0x90,
|
||||
0x00, 0x00, 0x4B, 0x00,
|
||||
0x00, 0x00, 0x4B, 0x60,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1mask
|
||||
Parameter Address = 29
|
||||
Parameter Value = 255
|
||||
Parameter Data :
|
||||
0x00, 0x00, 0x00, 0xFF,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1startgain
|
||||
Parameter Address = 27
|
||||
Parameter Value = 1.00135803222656E-05
|
||||
Parameter Data :
|
||||
0x00, 0x00, 0x00, 0x54,
|
||||
|
||||
|
||||
|
||||
Cell Name = ChimeWG1
|
||||
Parameter Name = Optimized2ChimeAlgWGainGUI1lowestgain
|
||||
Parameter Address = 28
|
||||
Parameter Value = 1.19209289550781E-07
|
||||
Parameter Data :
|
||||
0x00, 0x00, 0x00, 0x01,
|
||||
|
||||
|
||||
|
||||
Cell Name = None - Framework
|
||||
Parameter Name = NonModRamAlloc
|
||||
Parameter Address = 0
|
||||
@@ -72,6 +213,31 @@ See also H2201_V1.hex file
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x03 ,
|
||||
0x00 , 0x00 , 0x03 , 0x90 ,
|
||||
0x00 , 0x00 , 0x3B , 0x40 ,
|
||||
0x00 , 0x00 , 0x4B , 0x00 ,
|
||||
0x00 , 0x00 , 0x4B , 0x60 ,
|
||||
0x00 , 0x00 , 0x00 , 0x02 ,
|
||||
0x00 , 0x00 , 0x03 , 0x90 ,
|
||||
0x00 , 0x00 , 0x4B , 0x00 ,
|
||||
0x00 , 0x00 , 0x4B , 0x60 ,
|
||||
0x00 , 0x80 , 0x8C , 0xDC ,
|
||||
0x00 , 0x80 , 0x00 , 0x3D ,
|
||||
0x00 , 0x7F , 0xDF , 0x60 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x1B , 0x4F ,
|
||||
0x00 , 0x00 , 0x1B , 0x4F ,
|
||||
0x00 , 0x81 , 0xA4 , 0x78 ,
|
||||
0x00 , 0x7F , 0xE7 , 0x0D ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x00 , 0x00 , 0x54 ,
|
||||
0x00 , 0x00 , 0x00 , 0x01 ,
|
||||
0x00 , 0x00 , 0x00 , 0xFF ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
0x00 , 0x80 , 0x00 , 0x00 ,
|
||||
@@ -88,6 +254,31 @@ Parameter data for: IC1 (Binary format starting at parameter address 0)
|
||||
00000000 00000000 00000000 00000000
|
||||
00000000 00000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 00000000 00000000 00000011
|
||||
00000000 00000000 00000011 10010000
|
||||
00000000 00000000 00111011 01000000
|
||||
00000000 00000000 01001011 00000000
|
||||
00000000 00000000 01001011 01100000
|
||||
00000000 00000000 00000000 00000010
|
||||
00000000 00000000 00000011 10010000
|
||||
00000000 00000000 01001011 00000000
|
||||
00000000 00000000 01001011 01100000
|
||||
00000000 10000000 10001100 11011100
|
||||
00000000 10000000 00000000 00111101
|
||||
00000000 01111111 11011111 01100000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 00000000 00011011 01001111
|
||||
00000000 00000000 00011011 01001111
|
||||
00000000 10000001 10100100 01111000
|
||||
00000000 01111111 11100111 00001101
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 00000000 00000000 01010100
|
||||
00000000 00000000 00000000 00000001
|
||||
00000000 00000000 00000000 11111111
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
00000000 10000000 00000000 00000000
|
||||
|
||||
File diff suppressed because one or more lines are too long
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC1.h
|
||||
*
|
||||
* Created: Tuesday, April 26, 2022 9:47:52 AM
|
||||
* Created: Monday, May 2, 2022 9:54:40 AM
|
||||
* Description: H2201_V1:IC1 program data.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
@@ -26,7 +26,7 @@
|
||||
#define DEVICE_ADDR_IC1 0x70
|
||||
|
||||
/* DSP Program Data */
|
||||
#define PROGRAM_SIZE_IC1 315
|
||||
#define PROGRAM_SIZE_IC1 835
|
||||
#define PROGRAM_ADDR_IC1 2048
|
||||
ADI_REG_TYPE Program_Data_IC1[PROGRAM_SIZE_IC1] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
@@ -71,21 +71,125 @@ ADI_REG_TYPE Program_Data_IC1[PROGRAM_SIZE_IC1] = {
|
||||
0x00, 0x10, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x2D, 0x08, 0x20, 0x00,
|
||||
0x00, 0x18, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x09, 0x22, 0x00,
|
||||
0xFF, 0xE8, 0x08, 0x20, 0x00,
|
||||
0x00, 0x20, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x08, 0x0A, 0x20, 0x00,
|
||||
0x00, 0x18, 0x0B, 0x22, 0x00,
|
||||
0x00, 0x28, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x0C, 0x20, 0x00,
|
||||
0x00, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x20, 0x0D, 0x20, 0x00,
|
||||
0xFF, 0xED, 0x1F, 0x20, 0x00,
|
||||
0x00, 0x35, 0x08, 0x22, 0x00,
|
||||
0x00, 0x38, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x25, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x26,
|
||||
0x00, 0x38, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x40, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x0A, 0x21, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x22, 0x48,
|
||||
0x00, 0x45, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xFD, 0x08, 0x22, 0x27,
|
||||
0x00, 0x48, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x4D, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x09, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x09, 0x20, 0x00,
|
||||
0x00, 0x4D, 0x08, 0x20, 0x27,
|
||||
0x00, 0x48, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x25, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x4D, 0x08, 0x20, 0x26,
|
||||
0x00, 0x48, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xE8, 0x16, 0x20, 0x00,
|
||||
0x00, 0x75, 0x08, 0x20, 0x26,
|
||||
0x00, 0x70, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x75, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x17, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x17, 0x20, 0x00,
|
||||
0x00, 0x75, 0x08, 0x20, 0x25,
|
||||
0x00, 0x70, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x48, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x60, 0x12, 0x21, 0x00,
|
||||
0x00, 0x70, 0x12, 0x35, 0x00,
|
||||
0x00, 0x78, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x68, 0x00, 0xF2, 0x00,
|
||||
0x00, 0x50, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x0F, 0x21, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x22, 0x48,
|
||||
0x00, 0x55, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xFD, 0x08, 0x22, 0x27,
|
||||
0x00, 0x58, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x5D, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x0E, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x0E, 0x20, 0x00,
|
||||
0x00, 0x5D, 0x08, 0x20, 0x27,
|
||||
0x00, 0x58, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x25, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x5D, 0x08, 0x20, 0x26,
|
||||
0x00, 0x58, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xE8, 0x1B, 0x20, 0x00,
|
||||
0x00, 0x95, 0x08, 0x20, 0x26,
|
||||
0x00, 0x90, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x95, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x1C, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x1C, 0x20, 0x00,
|
||||
0x00, 0x95, 0x08, 0x20, 0x25,
|
||||
0x00, 0x90, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x58, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x18, 0x21, 0x00,
|
||||
0x00, 0x90, 0x18, 0x35, 0x00,
|
||||
0x00, 0x98, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x88, 0x00, 0xF2, 0x00,
|
||||
0x00, 0xB5, 0x1F, 0x20, 0x00,
|
||||
0x00, 0xA5, 0x08, 0x22, 0x00,
|
||||
0x00, 0x7D, 0x18, 0x22, 0x00,
|
||||
0x00, 0x00, 0x1D, 0xA0, 0x00,
|
||||
0x00, 0xA8, 0x00, 0xEA, 0x00,
|
||||
0x00, 0xB8, 0x00, 0xF2, 0x00,
|
||||
0x00, 0xA8, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x04, 0x01, 0xA1, 0x00,
|
||||
0xFF, 0xE5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x04, 0x00, 0xA1, 0x00,
|
||||
0xFF, 0xE5, 0x08, 0x22, 0x40,
|
||||
0x00, 0xC0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0xB8, 0x00, 0xC0, 0x00,
|
||||
0x00, 0xC7, 0xFF, 0x20, 0x00,
|
||||
0xFF, 0xE5, 0x08, 0x22, 0x00,
|
||||
0x00, 0xC8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0xC8, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x9F, 0xFF, 0x20, 0x00,
|
||||
0x00, 0x28, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x1E, 0x20, 0x00,
|
||||
0x00, 0xD0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x1E, 0x20, 0x00,
|
||||
0x00, 0xD8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x1F, 0x20, 0x00,
|
||||
0x00, 0x10, 0x20, 0x22, 0x00,
|
||||
0x00, 0xD0, 0x21, 0x22, 0x00,
|
||||
0x00, 0xE0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x08, 0x22, 0x20, 0x00,
|
||||
0x00, 0x18, 0x23, 0x22, 0x00,
|
||||
0x00, 0xD8, 0x24, 0x22, 0x00,
|
||||
0x00, 0xE8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0xE8, 0x25, 0x20, 0x00,
|
||||
0x00, 0xF0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0xE0, 0x26, 0x20, 0x00,
|
||||
0x00, 0xF8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0xFD, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x35, 0x08, 0x20, 0x00,
|
||||
0x00, 0xF5, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0x00, 0x00,
|
||||
@@ -95,21 +199,48 @@ ADI_REG_TYPE Program_Data_IC1[PROGRAM_SIZE_IC1] = {
|
||||
};
|
||||
|
||||
/* DSP Parameter (Coefficient) Data */
|
||||
#define PARAM_SIZE_IC1 56
|
||||
#define PARAM_SIZE_IC1 156
|
||||
#define PARAM_ADDR_IC1 0
|
||||
ADI_REG_TYPE Param_Data_IC1[PARAM_SIZE_IC1] = {
|
||||
0x00, 0x00, 0x10, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00, 0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00,
|
||||
0x80, 0x00, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00,
|
||||
0x00, 0x00, 0x10, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x03, 0x90,
|
||||
0x00, 0x00, 0x3B, 0x40,
|
||||
0x00, 0x00, 0x4B, 0x00,
|
||||
0x00, 0x00, 0x4B, 0x60,
|
||||
0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x03, 0x90,
|
||||
0x00, 0x00, 0x4B, 0x00,
|
||||
0x00, 0x00, 0x4B, 0x60,
|
||||
0x00, 0x80, 0x8C, 0xDC,
|
||||
0x00, 0x80, 0x00, 0x3D,
|
||||
0x00, 0x7F, 0xDF, 0x60,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x1B, 0x4F,
|
||||
0x00, 0x00, 0x1B, 0x4F,
|
||||
0x00, 0x81, 0xA4, 0x78,
|
||||
0x00, 0x7F, 0xE7, 0x0D,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x54,
|
||||
0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0xFF,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
};
|
||||
|
||||
|
||||
@@ -212,7 +343,7 @@ ADI_REG_TYPE R21_DSP_ENABLE_REGISTER_IC1_Default[REG_DSP_ENABLE_REGISTER_IC1_BYT
|
||||
/* Register Default - IC1.CRC Registers */
|
||||
#define R22_CRC_REGISTERS_IC1_SIZE 5
|
||||
ADI_REG_TYPE R22_CRC_REGISTERS_IC1_Default[R22_CRC_REGISTERS_IC1_SIZE] = {
|
||||
0x7F, 0x7F, 0x60, 0x7F, 0x01
|
||||
0x37, 0x43, 0x61, 0x7C, 0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC1.GPIO Registers */
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC1_PARAM.h
|
||||
*
|
||||
* Created: Tuesday, April 26, 2022 9:47:52 AM
|
||||
* Created: Monday, May 2, 2022 9:54:40 AM
|
||||
* Description: H2201_V1:IC1 parameter RAM definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
@@ -28,34 +28,146 @@
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(4096)
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
|
||||
/* Module Switch1 - On/Off Switch*/
|
||||
#define MOD_SWITCH1_COUNT 1
|
||||
#define MOD_SWITCH1_DEVICE "IC1"
|
||||
#define MOD_SWITCH1_ISON_ADDR 8
|
||||
#define MOD_SWITCH1_ISON_FIXPT 0x00800000
|
||||
#define MOD_SWITCH1_ISON_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_SWITCH1_ISON_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module ChimeWG1 - Chime Freq-Gain*/
|
||||
#define MOD_CHIMEWG1_COUNT 21
|
||||
#define MOD_CHIMEWG1_DEVICE "IC1"
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFPOINTSINTABLE_ADDR 9
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFPOINTSINTABLE_FIXPT 0x00000003
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFPOINTSINTABLE_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(3)
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFPOINTSINTABLE_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE0_ADDR 10
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE0_FIXPT 0x00000390
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE0_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(912)
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE0_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE1_ADDR 11
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE1_FIXPT 0x00003B40
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE1_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(15168)
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE1_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE2_ADDR 12
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE2_FIXPT 0x00004B00
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE2_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(19200)
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE2_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE3_ADDR 13
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE3_FIXPT 0x00004B60
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE3_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(19296)
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE3_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFGAINPOINTSINTABLE_ADDR 14
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFGAINPOINTSINTABLE_FIXPT 0x00000002
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFGAINPOINTSINTABLE_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(2)
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFGAINPOINTSINTABLE_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING0_ADDR 15
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING0_FIXPT 0x00000390
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING0_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(912)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING0_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING1_ADDR 16
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING1_FIXPT 0x00004B00
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING1_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(19200)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING1_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING2_ADDR 17
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING2_FIXPT 0x00004B60
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING2_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(19296)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING2_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES0_ADDR 18
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES0_FIXPT 0x00808CDC
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES0_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.00429871197835)
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES0_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES1_ADDR 19
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES1_FIXPT 0x0080003D
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.00000732045436)
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES2_ADDR 20
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES2_FIXPT 0x007FDF60
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES2_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.999004369228288)
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES2_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES3_ADDR 21
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES3_FIXPT 0x00800000
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES3_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES3_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGFREQ_ADDR 22
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGFREQ_FIXPT 0x00001B4E
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGFREQ_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.000833333333333333)
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGFREQ_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDFREQ_ADDR 23
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDFREQ_FIXPT 0x00001B4E
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDFREQ_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.000833333333333333)
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDFREQ_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS0_ADDR 24
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS0_FIXPT 0x0081A478
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS0_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.01283168856871)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS0_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS1_ADDR 25
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS1_FIXPT 0x007FE70C
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.999238553400038)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS2_ADDR 26
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS2_FIXPT 0x00800000
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS2_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS2_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGGAIN_ADDR 27
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGGAIN_FIXPT 0x00000053
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGGAIN_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1E-05)
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGGAIN_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDGAIN_ADDR 28
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDGAIN_FIXPT 0x00000000
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDGAIN_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1E-07)
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDGAIN_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_MASK_ADDR 29
|
||||
#define MOD_CHIMEWG1_ALG0_MASK_FIXPT 0x000000FF
|
||||
#define MOD_CHIMEWG1_ALG0_MASK_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(255)
|
||||
#define MOD_CHIMEWG1_ALG0_MASK_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
|
||||
/* Module S Splitter1 - Single Control Splitter*/
|
||||
#define MOD_SSPLITTER1_COUNT 1
|
||||
#define MOD_SSPLITTER1_DEVICE "IC1"
|
||||
#define MOD_SSPLITTER1_SINGLECTRLSPLIT1_ADDR 30
|
||||
#define MOD_SSPLITTER1_SINGLECTRLSPLIT1_FIXPT 0x00800000
|
||||
#define MOD_SSPLITTER1_SINGLECTRLSPLIT1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_SSPLITTER1_SINGLECTRLSPLIT1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Left Mixer - NxM Mixer*/
|
||||
#define MOD_LEFTMIXER_COUNT 2
|
||||
#define MOD_LEFTMIXER_COUNT 3
|
||||
#define MOD_LEFTMIXER_DEVICE "IC1"
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_ADDR 8
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_ADDR 31
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_FIXPT 0x00800000
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_ADDR 9
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_ADDR 32
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_FIXPT 0x00800000
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10002_ADDR 33
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10002_FIXPT 0x00800000
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10002_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10002_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Right Mixer - NxM Mixer*/
|
||||
#define MOD_RIGHTMIXER_COUNT 2
|
||||
#define MOD_RIGHTMIXER_COUNT 3
|
||||
#define MOD_RIGHTMIXER_DEVICE "IC1"
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_ADDR 10
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_ADDR 34
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_ADDR 11
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_ADDR 35
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20002_ADDR 36
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20002_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20002_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20002_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Right Master - Single Volume*/
|
||||
#define MOD_RIGHTMASTER_COUNT 1
|
||||
#define MOD_RIGHTMASTER_DEVICE "IC1"
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_ADDR 12
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_ADDR 37
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
@@ -63,7 +175,7 @@
|
||||
/* Module Left Master - Single Volume*/
|
||||
#define MOD_LEFTMASTER_COUNT 1
|
||||
#define MOD_LEFTMASTER_DEVICE "IC1"
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_ADDR 13
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_ADDR 38
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_FIXPT 0x00800000
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC1_REG.h
|
||||
*
|
||||
* Created: Tuesday, April 26, 2022 9:47:52 AM
|
||||
* Created: Monday, May 2, 2022 9:54:40 AM
|
||||
* Description: H2201_V1:IC1 control register definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
@@ -248,22 +248,22 @@
|
||||
/* CRC Ideal_1 - Registers (IC1) */
|
||||
#define REG_CRC_IDEAL_1_IC1_ADDR 0x40C0
|
||||
#define REG_CRC_IDEAL_1_IC1_BYTE 1
|
||||
#define REG_CRC_IDEAL_1_IC1_VALUE 0x7F
|
||||
#define REG_CRC_IDEAL_1_IC1_VALUE 0x37
|
||||
|
||||
/* CRC Ideal_2 - Registers (IC1) */
|
||||
#define REG_CRC_IDEAL_2_IC1_ADDR 0x40C1
|
||||
#define REG_CRC_IDEAL_2_IC1_BYTE 1
|
||||
#define REG_CRC_IDEAL_2_IC1_VALUE 0x7F
|
||||
#define REG_CRC_IDEAL_2_IC1_VALUE 0x43
|
||||
|
||||
/* CRC Ideal_3 - Registers (IC1) */
|
||||
#define REG_CRC_IDEAL_3_IC1_ADDR 0x40C2
|
||||
#define REG_CRC_IDEAL_3_IC1_BYTE 1
|
||||
#define REG_CRC_IDEAL_3_IC1_VALUE 0x60
|
||||
#define REG_CRC_IDEAL_3_IC1_VALUE 0x61
|
||||
|
||||
/* CRC Ideal_4 - Registers (IC1) */
|
||||
#define REG_CRC_IDEAL_4_IC1_ADDR 0x40C3
|
||||
#define REG_CRC_IDEAL_4_IC1_BYTE 1
|
||||
#define REG_CRC_IDEAL_4_IC1_VALUE 0x7F
|
||||
#define REG_CRC_IDEAL_4_IC1_VALUE 0x7C
|
||||
|
||||
/* CRC Enable - Registers (IC1) */
|
||||
#define REG_CRC_ENABLE_IC1_ADDR 0x40C4
|
||||
@@ -875,22 +875,22 @@
|
||||
#define R44_DEJITTER_IC1_SHIFT 0
|
||||
|
||||
/* CRC Ideal_1 (IC1) */
|
||||
#define R45_CRC_IDEAL_1_IC1 0x7F /* 01111111b [7:0] */
|
||||
#define R45_CRC_IDEAL_1_IC1 0x37 /* 00110111b [7:0] */
|
||||
#define R45_CRC_IDEAL_1_IC1_MASK 0xFF
|
||||
#define R45_CRC_IDEAL_1_IC1_SHIFT 0
|
||||
|
||||
/* CRC Ideal_2 (IC1) */
|
||||
#define R46_CRC_IDEAL_2_IC1 0x7F /* 01111111b [7:0] */
|
||||
#define R46_CRC_IDEAL_2_IC1 0x43 /* 01000011b [7:0] */
|
||||
#define R46_CRC_IDEAL_2_IC1_MASK 0xFF
|
||||
#define R46_CRC_IDEAL_2_IC1_SHIFT 0
|
||||
|
||||
/* CRC Ideal_3 (IC1) */
|
||||
#define R47_CRC_IDEAL_3_IC1 0x60 /* 01100000b [7:0] */
|
||||
#define R47_CRC_IDEAL_3_IC1 0x61 /* 01100001b [7:0] */
|
||||
#define R47_CRC_IDEAL_3_IC1_MASK 0xFF
|
||||
#define R47_CRC_IDEAL_3_IC1_SHIFT 0
|
||||
|
||||
/* CRC Ideal_4 (IC1) */
|
||||
#define R48_CRC_IDEAL_4_IC1 0x7F /* 01111111b [7:0] */
|
||||
#define R48_CRC_IDEAL_4_IC1 0x7C /* 01111100b [7:0] */
|
||||
#define R48_CRC_IDEAL_4_IC1_MASK 0xFF
|
||||
#define R48_CRC_IDEAL_4_IC1_SHIFT 0
|
||||
|
||||
|
||||
@@ -23,14 +23,28 @@
|
||||
<Link pin="O_C267_A0_P3_out" dir="out" link="Link4" />
|
||||
<Link pin="O_C267_A0_P4_out" dir="out" link="Link5" />
|
||||
</Algorithm>
|
||||
<Algorithm name="NxNMixer1940Alg1" friendlyname="NxM Ctrl Mixer " cell="Left Mixer " location="{X=346, Y=205} " Growth="2 " GrowthB="1">
|
||||
<Algorithm name="SwitchAlg1" friendlyname="OnOff 5_23 Output " cell="Switch1 " location="{X=148, Y=505} " Growth="0 " GrowthB="0">
|
||||
<Link pin="O_C33_A0_P1_out" dir="out" link="Link11" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Optimized2ChimeAlgWGainGUI1" friendlyname="Chime Freq - Gain " cell="ChimeWG1 " location="{X=265, Y=518} " Growth="0 " GrowthB="0">
|
||||
<Link pin="I_C49_A0_P1_in" dir="in" link="Link11" />
|
||||
<Link pin="O_C49_A0_P2_out" dir="out" link="Link10" />
|
||||
</Algorithm>
|
||||
<Algorithm name="SingleCtrlSplit1" friendlyname="Splitter Single " cell="S Splitter1 " location="{X=376, Y=489} " Growth="2 " GrowthB="0">
|
||||
<Link pin="I_C4_A0_P1_in" dir="in" link="Link10" />
|
||||
<Link pin="O_C4_A0_P2_out" dir="out" link="Link9" />
|
||||
<Link pin="O_C4_A0_P3_out" dir="out" link="Link8" />
|
||||
</Algorithm>
|
||||
<Algorithm name="NxNMixer1940Alg1" friendlyname="NxM Ctrl Mixer " cell="Left Mixer " location="{X=563, Y=194} " Growth="3 " GrowthB="1">
|
||||
<Link pin="I_C13_A0_P2_in" dir="in" link="Link2" />
|
||||
<Link pin="I_C13_A0_P3_in" dir="in" link="Link4" />
|
||||
<Link pin="I_C13_A0_P4_in" dir="in" link="Link9" />
|
||||
<Link pin="O_C13_A0_P1_out" dir="out" link="Link7" />
|
||||
</Algorithm>
|
||||
<Algorithm name="NxNMixer1940Alg2" friendlyname="NxM Ctrl Mixer " cell="Right Mixer " location="{X=350, Y=399} " Growth="2 " GrowthB="1">
|
||||
<Algorithm name="NxNMixer1940Alg2" friendlyname="NxM Ctrl Mixer " cell="Right Mixer " location="{X=591, Y=380} " Growth="3 " GrowthB="1">
|
||||
<Link pin="I_C19_A0_P2_in" dir="in" link="Link3" />
|
||||
<Link pin="I_C19_A0_P3_in" dir="in" link="Link5" />
|
||||
<Link pin="I_C19_A0_P4_in" dir="in" link="Link8" />
|
||||
<Link pin="O_C19_A0_P1_out" dir="out" link="Link6" />
|
||||
</Algorithm>
|
||||
<Algorithm name="Gain1940AlgNS1" friendlyname="Gain (no slew) " cell="Right Master " location="{X=808, Y=311} " Growth="0 " GrowthB="0">
|
||||
|
||||
@@ -31,8 +31,8 @@
|
||||
3,
|
||||
3,
|
||||
4,
|
||||
317,
|
||||
58,
|
||||
837,
|
||||
158,
|
||||
3,
|
||||
3,
|
||||
3,
|
||||
|
||||
@@ -861,7 +861,7 @@
|
||||
0x40, 0xF5, /* (21) IC1.DSP ON Register */
|
||||
0x01,
|
||||
0x40, 0xC0, /* (22) IC1.CRC Registers */
|
||||
0x7F, 0x7F, 0x60, 0x7F, 0x01,
|
||||
0x37, 0x43, 0x61, 0x7C, 0x01,
|
||||
0x40, 0xC6, /* (23) IC1.GPIO Registers */
|
||||
0x07, 0x07, 0x00, 0x00,
|
||||
0x40, 0xE9, /* (24) IC1.Non Modulo Registers */
|
||||
@@ -925,21 +925,125 @@
|
||||
0x00, 0x10, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x2D, 0x08, 0x20, 0x00,
|
||||
0x00, 0x18, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x09, 0x22, 0x00,
|
||||
0xFF, 0xE8, 0x08, 0x20, 0x00,
|
||||
0x00, 0x20, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x08, 0x0A, 0x20, 0x00,
|
||||
0x00, 0x18, 0x0B, 0x22, 0x00,
|
||||
0x00, 0x28, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x0C, 0x20, 0x00,
|
||||
0x00, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x20, 0x0D, 0x20, 0x00,
|
||||
0xFF, 0xED, 0x1F, 0x20, 0x00,
|
||||
0x00, 0x35, 0x08, 0x22, 0x00,
|
||||
0x00, 0x38, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x25, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x26,
|
||||
0x00, 0x38, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x40, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x0A, 0x21, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x22, 0x48,
|
||||
0x00, 0x45, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xFD, 0x08, 0x22, 0x27,
|
||||
0x00, 0x48, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x4D, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x09, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x09, 0x20, 0x00,
|
||||
0x00, 0x4D, 0x08, 0x20, 0x27,
|
||||
0x00, 0x48, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x25, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x4D, 0x08, 0x20, 0x26,
|
||||
0x00, 0x48, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xE8, 0x16, 0x20, 0x00,
|
||||
0x00, 0x75, 0x08, 0x20, 0x26,
|
||||
0x00, 0x70, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x75, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x17, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x17, 0x20, 0x00,
|
||||
0x00, 0x75, 0x08, 0x20, 0x25,
|
||||
0x00, 0x70, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x48, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x60, 0x12, 0x21, 0x00,
|
||||
0x00, 0x70, 0x12, 0x35, 0x00,
|
||||
0x00, 0x78, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x68, 0x00, 0xF2, 0x00,
|
||||
0x00, 0x50, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x0F, 0x21, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x22, 0x48,
|
||||
0x00, 0x55, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xFD, 0x08, 0x22, 0x27,
|
||||
0x00, 0x58, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x5D, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x0E, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x0E, 0x20, 0x00,
|
||||
0x00, 0x5D, 0x08, 0x20, 0x27,
|
||||
0x00, 0x58, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x25, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x5D, 0x08, 0x20, 0x26,
|
||||
0x00, 0x58, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xE8, 0x1B, 0x20, 0x00,
|
||||
0x00, 0x95, 0x08, 0x20, 0x26,
|
||||
0x00, 0x90, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x95, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x1C, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x1C, 0x20, 0x00,
|
||||
0x00, 0x95, 0x08, 0x20, 0x25,
|
||||
0x00, 0x90, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x58, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x18, 0x21, 0x00,
|
||||
0x00, 0x90, 0x18, 0x35, 0x00,
|
||||
0x00, 0x98, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x88, 0x00, 0xF2, 0x00,
|
||||
0x00, 0xB5, 0x1F, 0x20, 0x00,
|
||||
0x00, 0xA5, 0x08, 0x22, 0x00,
|
||||
0x00, 0x7D, 0x18, 0x22, 0x00,
|
||||
0x00, 0x00, 0x1D, 0xA0, 0x00,
|
||||
0x00, 0xA8, 0x00, 0xEA, 0x00,
|
||||
0x00, 0xB8, 0x00, 0xF2, 0x00,
|
||||
0x00, 0xA8, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x04, 0x01, 0xA1, 0x00,
|
||||
0xFF, 0xE5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x04, 0x00, 0xA1, 0x00,
|
||||
0xFF, 0xE5, 0x08, 0x22, 0x40,
|
||||
0x00, 0xC0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0xB8, 0x00, 0xC0, 0x00,
|
||||
0x00, 0xC7, 0xFF, 0x20, 0x00,
|
||||
0xFF, 0xE5, 0x08, 0x22, 0x00,
|
||||
0x00, 0xC8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0xC8, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x9F, 0xFF, 0x20, 0x00,
|
||||
0x00, 0x28, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x1E, 0x20, 0x00,
|
||||
0x00, 0xD0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x1E, 0x20, 0x00,
|
||||
0x00, 0xD8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x1F, 0x20, 0x00,
|
||||
0x00, 0x10, 0x20, 0x22, 0x00,
|
||||
0x00, 0xD0, 0x21, 0x22, 0x00,
|
||||
0x00, 0xE0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x08, 0x22, 0x20, 0x00,
|
||||
0x00, 0x18, 0x23, 0x22, 0x00,
|
||||
0x00, 0xD8, 0x24, 0x22, 0x00,
|
||||
0x00, 0xE8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0xE8, 0x25, 0x20, 0x00,
|
||||
0x00, 0xF0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0xE0, 0x26, 0x20, 0x00,
|
||||
0x00, 0xF8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0xFD, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x35, 0x08, 0x20, 0x00,
|
||||
0x00, 0xF5, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0x00, 0x00,
|
||||
@@ -947,18 +1051,45 @@
|
||||
0xFE, 0xC0, 0x0F, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, /* (34) Param */
|
||||
0x00, 0x00, 0x10, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00, 0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00, 0x00,
|
||||
0x80, 0x00, 0x00, 0x00, 0x80,
|
||||
0x00, 0x00, 0x00, 0x80, 0x00,
|
||||
0x00,
|
||||
0x00, 0x00, 0x10, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x03, 0x90,
|
||||
0x00, 0x00, 0x3B, 0x40,
|
||||
0x00, 0x00, 0x4B, 0x00,
|
||||
0x00, 0x00, 0x4B, 0x60,
|
||||
0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x03, 0x90,
|
||||
0x00, 0x00, 0x4B, 0x00,
|
||||
0x00, 0x00, 0x4B, 0x60,
|
||||
0x00, 0x80, 0x8C, 0xDC,
|
||||
0x00, 0x80, 0x00, 0x3D,
|
||||
0x00, 0x7F, 0xDF, 0x60,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x1B, 0x4F,
|
||||
0x00, 0x00, 0x1B, 0x4F,
|
||||
0x00, 0x81, 0xA4, 0x78,
|
||||
0x00, 0x7F, 0xE7, 0x0D,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x54,
|
||||
0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0xFF,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x40, 0xEB, /* (35) IC1.Sample Rate Setting */
|
||||
0x00,
|
||||
0x40, 0xF6, /* (36) IC1.DSP Run Register */
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* File: defines.h
|
||||
*
|
||||
* Created: Tuesday, April 26, 2022 9:47:52 AM
|
||||
* Created: Monday, May 2, 2022 9:54:40 AM
|
||||
* Description: H2201_V1 IC default download data definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
@@ -19,7 +19,7 @@
|
||||
#ifndef __DEFINES_H__
|
||||
#define __DEFINES_H__
|
||||
|
||||
#define BufferSize_IC1 4625
|
||||
#define BufferSize_IC1 5245
|
||||
#define NumTransactions_IC1 39
|
||||
|
||||
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
idf_component_register(SRCS "H2201_i2c.c" "h2201_app.c" "H2201_avrcp.c" "H2201_a2dp.c" "H2201_i2s.c"
|
||||
idf_component_register(SRCS "H2201_buttons.c" "H2201_i2c.c" "h2201_app.c" "H2201_avrcp.c" "H2201_a2dp.c" "H2201_i2s.c"
|
||||
|
||||
"main.c"
|
||||
INCLUDE_DIRS ".")
|
||||
|
||||
471
ESP32/main/H2201_V1_IC1.h
Normal file
471
ESP32/main/H2201_V1_IC1.h
Normal file
@@ -0,0 +1,471 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC1.h
|
||||
*
|
||||
* Created: Monday, May 2, 2022 9:54:40 AM
|
||||
* Description: H2201_V1:IC1 program data.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __H2201_V1_IC1_H__
|
||||
#define __H2201_V1_IC1_H__
|
||||
|
||||
#include "SigmaStudioFW.h"
|
||||
#include "H2201_V1_IC1_REG.h"
|
||||
|
||||
#define DEVICE_ARCHITECTURE_IC1 "ADAU176x"
|
||||
#define DEVICE_ADDR_IC1 0x70
|
||||
|
||||
/* DSP Program Data */
|
||||
#define PROGRAM_SIZE_IC1 835
|
||||
#define PROGRAM_ADDR_IC1 2048
|
||||
ADI_REG_TYPE Program_Data_IC1[PROGRAM_SIZE_IC1] = {
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE0, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x34, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x2C, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x54, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x5C, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0xFF, 0x38, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x80, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE8, 0x0C, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x07, 0x20, 0x08,
|
||||
0x00, 0x00, 0x06, 0xA0, 0x00,
|
||||
0xFF, 0xE0, 0x00, 0xC0, 0x00,
|
||||
0xFF, 0x80, 0x07, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xC0, 0x22, 0x00, 0x27,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xE8, 0x1E, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x01, 0x20, 0x00,
|
||||
0xFF, 0xD8, 0x01, 0x03, 0x00,
|
||||
0x00, 0x07, 0xC6, 0x00, 0x00,
|
||||
0xFF, 0x08, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xF4, 0x00, 0x20, 0x00,
|
||||
0xFF, 0xD8, 0x07, 0x02, 0x00,
|
||||
0xFD, 0xA5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x00, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0xAD, 0x08, 0x20, 0x00,
|
||||
0x00, 0x08, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x25, 0x08, 0x20, 0x00,
|
||||
0x00, 0x10, 0x00, 0xE2, 0x00,
|
||||
0xFD, 0x2D, 0x08, 0x20, 0x00,
|
||||
0x00, 0x18, 0x00, 0xE2, 0x00,
|
||||
0xFF, 0xE8, 0x08, 0x20, 0x00,
|
||||
0x00, 0x20, 0x00, 0xE2, 0x00,
|
||||
0xFF, 0xED, 0x1F, 0x20, 0x00,
|
||||
0x00, 0x35, 0x08, 0x22, 0x00,
|
||||
0x00, 0x38, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x25, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x26,
|
||||
0x00, 0x38, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x40, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x0A, 0x21, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x22, 0x48,
|
||||
0x00, 0x45, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xFD, 0x08, 0x22, 0x27,
|
||||
0x00, 0x48, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x4D, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x09, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x09, 0x20, 0x00,
|
||||
0x00, 0x4D, 0x08, 0x20, 0x27,
|
||||
0x00, 0x48, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x25, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x4D, 0x08, 0x20, 0x26,
|
||||
0x00, 0x48, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xE8, 0x16, 0x20, 0x00,
|
||||
0x00, 0x75, 0x08, 0x20, 0x26,
|
||||
0x00, 0x70, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x75, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x17, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x17, 0x20, 0x00,
|
||||
0x00, 0x75, 0x08, 0x20, 0x25,
|
||||
0x00, 0x70, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x48, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x60, 0x12, 0x21, 0x00,
|
||||
0x00, 0x70, 0x12, 0x35, 0x00,
|
||||
0x00, 0x78, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x68, 0x00, 0xF2, 0x00,
|
||||
0x00, 0x50, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFF, 0xE8, 0x0F, 0x21, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x22, 0x48,
|
||||
0x00, 0x55, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xFD, 0x08, 0x22, 0x27,
|
||||
0x00, 0x58, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x5D, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x0E, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x0E, 0x20, 0x00,
|
||||
0x00, 0x5D, 0x08, 0x20, 0x27,
|
||||
0x00, 0x58, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x25, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xF5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x5D, 0x08, 0x20, 0x26,
|
||||
0x00, 0x58, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x3D, 0x08, 0x20, 0x08,
|
||||
0xFF, 0xE8, 0x1B, 0x20, 0x00,
|
||||
0x00, 0x95, 0x08, 0x20, 0x26,
|
||||
0x00, 0x90, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x95, 0x08, 0x20, 0x00,
|
||||
0xFF, 0xE8, 0x1C, 0x22, 0x48,
|
||||
0xFF, 0xE8, 0x1C, 0x20, 0x00,
|
||||
0x00, 0x95, 0x08, 0x20, 0x25,
|
||||
0x00, 0x90, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x58, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x18, 0x21, 0x00,
|
||||
0x00, 0x90, 0x18, 0x35, 0x00,
|
||||
0x00, 0x98, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x88, 0x00, 0xF2, 0x00,
|
||||
0x00, 0xB5, 0x1F, 0x20, 0x00,
|
||||
0x00, 0xA5, 0x08, 0x22, 0x00,
|
||||
0x00, 0x7D, 0x18, 0x22, 0x00,
|
||||
0x00, 0x00, 0x1D, 0xA0, 0x00,
|
||||
0x00, 0xA8, 0x00, 0xEA, 0x00,
|
||||
0x00, 0xB8, 0x00, 0xF2, 0x00,
|
||||
0x00, 0xA8, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x04, 0x01, 0xA1, 0x00,
|
||||
0xFF, 0xE5, 0x08, 0x20, 0x00,
|
||||
0x00, 0x04, 0x00, 0xA1, 0x00,
|
||||
0xFF, 0xE5, 0x08, 0x22, 0x40,
|
||||
0x00, 0xC0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0xB8, 0x00, 0xC0, 0x00,
|
||||
0x00, 0xC7, 0xFF, 0x20, 0x00,
|
||||
0xFF, 0xE5, 0x08, 0x22, 0x00,
|
||||
0x00, 0xC8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0xC8, 0x00, 0xC0, 0x00,
|
||||
0x00, 0x9F, 0xFF, 0x20, 0x00,
|
||||
0x00, 0x28, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x1E, 0x20, 0x00,
|
||||
0x00, 0xD0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x28, 0x1E, 0x20, 0x00,
|
||||
0x00, 0xD8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x1F, 0x20, 0x00,
|
||||
0x00, 0x10, 0x20, 0x22, 0x00,
|
||||
0x00, 0xD0, 0x21, 0x22, 0x00,
|
||||
0x00, 0xE0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x08, 0x22, 0x20, 0x00,
|
||||
0x00, 0x18, 0x23, 0x22, 0x00,
|
||||
0x00, 0xD8, 0x24, 0x22, 0x00,
|
||||
0x00, 0xE8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0xE8, 0x25, 0x20, 0x00,
|
||||
0x00, 0xF0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0xE0, 0x26, 0x20, 0x00,
|
||||
0x00, 0xF8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0xFD, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB0, 0x00, 0xE2, 0x00,
|
||||
0x00, 0xF5, 0x08, 0x20, 0x00,
|
||||
0xFD, 0xB8, 0x00, 0xE2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0x30, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0xFE, 0xC0, 0x0F, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
};
|
||||
|
||||
/* DSP Parameter (Coefficient) Data */
|
||||
#define PARAM_SIZE_IC1 156
|
||||
#define PARAM_ADDR_IC1 0
|
||||
ADI_REG_TYPE Param_Data_IC1[PARAM_SIZE_IC1] = {
|
||||
0x00, 0x00, 0x10, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x03,
|
||||
0x00, 0x00, 0x03, 0x90,
|
||||
0x00, 0x00, 0x3B, 0x40,
|
||||
0x00, 0x00, 0x4B, 0x00,
|
||||
0x00, 0x00, 0x4B, 0x60,
|
||||
0x00, 0x00, 0x00, 0x02,
|
||||
0x00, 0x00, 0x03, 0x90,
|
||||
0x00, 0x00, 0x4B, 0x00,
|
||||
0x00, 0x00, 0x4B, 0x60,
|
||||
0x00, 0x80, 0x8C, 0xDC,
|
||||
0x00, 0x80, 0x00, 0x3D,
|
||||
0x00, 0x7F, 0xDF, 0x60,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x1B, 0x4F,
|
||||
0x00, 0x00, 0x1B, 0x4F,
|
||||
0x00, 0x81, 0xA4, 0x78,
|
||||
0x00, 0x7F, 0xE7, 0x0D,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x54,
|
||||
0x00, 0x00, 0x00, 0x01,
|
||||
0x00, 0x00, 0x00, 0xFF,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
0x00, 0x80, 0x00, 0x00,
|
||||
};
|
||||
|
||||
|
||||
/* Register Default - IC1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R0_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x7F
|
||||
};
|
||||
|
||||
/* Register Default - IC1.DSP Run Register */
|
||||
ADI_REG_TYPE R1_DSP_RUN_REGISTER_IC1_Default[REG_DSP_RUN_REGISTER_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Clock Control Register */
|
||||
ADI_REG_TYPE R2_CLKCTRLREGISTER_IC1_Default[REG_CLKCTRLREGISTER_IC1_BYTE] = {
|
||||
0x0F
|
||||
};
|
||||
|
||||
/* Register Default - IC1.PLL Control Register */
|
||||
ADI_REG_TYPE R3_PLLCRLREGISTER_IC1_Default[REG_PLLCRLREGISTER_IC1_BYTE] = {
|
||||
0x00, 0x01, 0x00, 0x00, 0x20, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Delay */
|
||||
#define R4_DELAY_IC1_ADDR 0x0
|
||||
#define R4_DELAY_IC1_SIZE 2
|
||||
ADI_REG_TYPE R4_DELAY_IC1_Default[R4_DELAY_IC1_SIZE] = {
|
||||
0x00, 0x64
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Serial Port Control Registers */
|
||||
#define R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_Default[R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.ALC Control Registers */
|
||||
#define R6_ALC_CONTROL_REGISTERS_IC1_SIZE 4
|
||||
ADI_REG_TYPE R6_ALC_CONTROL_REGISTERS_IC1_Default[R6_ALC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Microphone Control Register */
|
||||
ADI_REG_TYPE R7_MICCTRLREGISTER_IC1_Default[REG_MICCTRLREGISTER_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Record Input Signal Path Registers */
|
||||
#define R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE 8
|
||||
ADI_REG_TYPE R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_Default[R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x01, 0x05, 0x01, 0x05, 0x00, 0x00, 0x08
|
||||
};
|
||||
|
||||
/* Register Default - IC1.ADC Control Registers */
|
||||
#define R9_ADC_CONTROL_REGISTERS_IC1_SIZE 3
|
||||
ADI_REG_TYPE R9_ADC_CONTROL_REGISTERS_IC1_Default[R9_ADC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x13, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Playback Output Signal Path Registers */
|
||||
#define R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE 14
|
||||
ADI_REG_TYPE R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_Default[R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE] = {
|
||||
0x61, 0x00, 0x61, 0x00, 0x0A, 0x0A, 0x00, 0xE7, 0xE7, 0x02, 0x02, 0xE7, 0x00, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Converter Control Registers */
|
||||
#define R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R11_CONVERTER_CONTROL_REGISTERS_IC1_Default[R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.DAC Control Registers */
|
||||
#define R12_DAC_CONTROL_REGISTERS_IC1_SIZE 3
|
||||
ADI_REG_TYPE R12_DAC_CONTROL_REGISTERS_IC1_Default[R12_DAC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x03, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Serial Port Pad Control Registers */
|
||||
#define R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE 1
|
||||
ADI_REG_TYPE R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_Default[R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0xAA
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Communication Port Pad Control Registers */
|
||||
#define R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_Default[R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0xAA, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Jack Detect Pad Control Register */
|
||||
ADI_REG_TYPE R15_JACKREGISTER_IC1_Default[REG_JACKREGISTER_IC1_BYTE] = {
|
||||
0x08
|
||||
};
|
||||
|
||||
/* Register Default - IC1.DSP ON Register */
|
||||
ADI_REG_TYPE R21_DSP_ENABLE_REGISTER_IC1_Default[REG_DSP_ENABLE_REGISTER_IC1_BYTE] = {
|
||||
0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC1.CRC Registers */
|
||||
#define R22_CRC_REGISTERS_IC1_SIZE 5
|
||||
ADI_REG_TYPE R22_CRC_REGISTERS_IC1_Default[R22_CRC_REGISTERS_IC1_SIZE] = {
|
||||
0x37, 0x43, 0x61, 0x7C, 0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC1.GPIO Registers */
|
||||
#define R23_GPIO_REGISTERS_IC1_SIZE 4
|
||||
ADI_REG_TYPE R23_GPIO_REGISTERS_IC1_Default[R23_GPIO_REGISTERS_IC1_SIZE] = {
|
||||
0x07, 0x07, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Non Modulo Registers */
|
||||
#define R24_NON_MODULO_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R24_NON_MODULO_REGISTERS_IC1_Default[R24_NON_MODULO_REGISTERS_IC1_SIZE] = {
|
||||
0x10, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Watchdog Registers */
|
||||
#define R25_WATCHDOG_REGISTERS_IC1_SIZE 5
|
||||
ADI_REG_TYPE R25_WATCHDOG_REGISTERS_IC1_Default[R25_WATCHDOG_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x02, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Sampling Rate Setting Register */
|
||||
ADI_REG_TYPE R26_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x7F
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Routing Matrix Inputs Register */
|
||||
ADI_REG_TYPE R27_ROUTING_MATRIX_INPUTS_IC1_Default[REG_ROUTING_MATRIX_INPUTS_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Routing Matrix Outputs Register */
|
||||
ADI_REG_TYPE R28_ROUTING_MATRIX_OUTPUTS_IC1_Default[REG_ROUTING_MATRIX_OUTPUTS_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Serial Data Configuration Register */
|
||||
ADI_REG_TYPE R29_SERIAL_DATAGPIO_PIN_CONFIG_IC1_Default[REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.DSP Slew Mode Register */
|
||||
ADI_REG_TYPE R30_DSP_SLEW_MODES_IC1_Default[REG_DSP_SLEW_MODES_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Serial Port Sample Rate Register */
|
||||
ADI_REG_TYPE R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_Default[REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Clock Enable Registers */
|
||||
#define R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R32_CLOCK_ENABLE_REGISTERS_IC1_Default[R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE] = {
|
||||
0x7F, 0x03
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R35_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.DSP Run Register */
|
||||
ADI_REG_TYPE R36_DSP_RUN_REGISTER_IC1_Default[REG_DSP_RUN_REGISTER_IC1_BYTE] = {
|
||||
0x01
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R37_DEJITTER_REGISTER_CONTROL_IC1_Default[REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE] = {
|
||||
0x00
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R38_DEJITTER_REGISTER_CONTROL_IC1_Default[REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE] = {
|
||||
0x03
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Default Download
|
||||
*/
|
||||
#define DEFAULT_DOWNLOAD_SIZE_IC1 39
|
||||
|
||||
void default_download_IC1() {
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R0_SAMPLE_RATE_SETTING_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DSP_RUN_REGISTER_IC1_ADDR, REG_DSP_RUN_REGISTER_IC1_BYTE, R1_DSP_RUN_REGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_CLKCTRLREGISTER_IC1_ADDR, REG_CLKCTRLREGISTER_IC1_BYTE, R2_CLKCTRLREGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_PLLCRLREGISTER_IC1_ADDR, REG_PLLCRLREGISTER_IC1_BYTE, R3_PLLCRLREGISTER_IC1_Default );
|
||||
SIGMA_WRITE_DELAY( DEVICE_ADDR_IC1, R4_DELAY_IC1_SIZE, R4_DELAY_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SERIAL_PORT_CONTROL_0_IC1_ADDR , R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE, R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_ALC_CONTROL_0_IC1_ADDR , R6_ALC_CONTROL_REGISTERS_IC1_SIZE, R6_ALC_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_MICCTRLREGISTER_IC1_ADDR, REG_MICCTRLREGISTER_IC1_BYTE, R7_MICCTRLREGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_RECORD_PWR_MANAGEMENT_IC1_ADDR , R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE, R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_ADC_CONTROL_0_IC1_ADDR , R9_ADC_CONTROL_REGISTERS_IC1_SIZE, R9_ADC_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_PLAYBACK_MIXER_LEFT_CONTROL_0_IC1_ADDR , R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE, R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_CONVERTER_CTRL_0_IC1_ADDR , R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE, R11_CONVERTER_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DAC_CONTROL_0_IC1_ADDR , R12_DAC_CONTROL_REGISTERS_IC1_SIZE, R12_DAC_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SERIAL_PORT_PAD_CONTROL_0_IC1_ADDR , R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE, R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_COMM_PORT_PAD_CTRL_0_IC1_ADDR , R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE, R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_JACKREGISTER_IC1_ADDR, REG_JACKREGISTER_IC1_BYTE, R15_JACKREGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DSP_ENABLE_REGISTER_IC1_ADDR, REG_DSP_ENABLE_REGISTER_IC1_BYTE, R21_DSP_ENABLE_REGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_CRC_IDEAL_1_IC1_ADDR , R22_CRC_REGISTERS_IC1_SIZE, R22_CRC_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_GPIO_0_CONTROL_IC1_ADDR , R23_GPIO_REGISTERS_IC1_SIZE, R23_GPIO_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_NON_MODULO_RAM_1_IC1_ADDR , R24_NON_MODULO_REGISTERS_IC1_SIZE, R24_NON_MODULO_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_WATCHDOG_ENABLE_IC1_ADDR , R25_WATCHDOG_REGISTERS_IC1_SIZE, R25_WATCHDOG_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R26_SAMPLE_RATE_SETTING_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_ROUTING_MATRIX_INPUTS_IC1_ADDR, REG_ROUTING_MATRIX_INPUTS_IC1_BYTE, R27_ROUTING_MATRIX_INPUTS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_ROUTING_MATRIX_OUTPUTS_IC1_ADDR, REG_ROUTING_MATRIX_OUTPUTS_IC1_BYTE, R28_ROUTING_MATRIX_OUTPUTS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_ADDR, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_BYTE, R29_SERIAL_DATAGPIO_PIN_CONFIG_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DSP_SLEW_MODES_IC1_ADDR, REG_DSP_SLEW_MODES_IC1_BYTE, R30_DSP_SLEW_MODES_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_BYTE, R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_CLOCK_ENABLE_REG_0_IC1_ADDR , R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE, R32_CLOCK_ENABLE_REGISTERS_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, PARAM_ADDR_IC1, PARAM_SIZE_IC1, Param_Data_IC1 );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R35_SAMPLE_RATE_SETTING_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DSP_RUN_REGISTER_IC1_ADDR, REG_DSP_RUN_REGISTER_IC1_BYTE, R36_DSP_RUN_REGISTER_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DEJITTER_REGISTER_CONTROL_IC1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE, R37_DEJITTER_REGISTER_CONTROL_IC1_Default );
|
||||
SIGMA_WRITE_REGISTER_BLOCK( DEVICE_ADDR_IC1, REG_DEJITTER_REGISTER_CONTROL_IC1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE, R38_DEJITTER_REGISTER_CONTROL_IC1_Default );
|
||||
}
|
||||
|
||||
#endif
|
||||
183
ESP32/main/H2201_V1_IC1_PARAM.h
Normal file
183
ESP32/main/H2201_V1_IC1_PARAM.h
Normal file
@@ -0,0 +1,183 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC1_PARAM.h
|
||||
*
|
||||
* Created: Monday, May 2, 2022 9:54:40 AM
|
||||
* Description: H2201_V1:IC1 parameter RAM definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __H2201_V1_IC1_PARAM_H__
|
||||
#define __H2201_V1_IC1_PARAM_H__
|
||||
|
||||
|
||||
/* Module Modulo Size - Modulo Size*/
|
||||
#define MOD_MODULOSIZE_COUNT 1
|
||||
#define MOD_MODULOSIZE_DEVICE "IC1"
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_ADDR 0
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_FIXPT 0x00001000
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(4096)
|
||||
#define MOD_MODULOSIZE_MODULO_SIZE_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
|
||||
/* Module Switch1 - On/Off Switch*/
|
||||
#define MOD_SWITCH1_COUNT 1
|
||||
#define MOD_SWITCH1_DEVICE "IC1"
|
||||
#define MOD_SWITCH1_ISON_ADDR 8
|
||||
#define MOD_SWITCH1_ISON_FIXPT 0x00800000
|
||||
#define MOD_SWITCH1_ISON_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_SWITCH1_ISON_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module ChimeWG1 - Chime Freq-Gain*/
|
||||
#define MOD_CHIMEWG1_COUNT 21
|
||||
#define MOD_CHIMEWG1_DEVICE "IC1"
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFPOINTSINTABLE_ADDR 9
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFPOINTSINTABLE_FIXPT 0x00000003
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFPOINTSINTABLE_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(3)
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFPOINTSINTABLE_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE0_ADDR 10
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE0_FIXPT 0x00000390
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE0_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(912)
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE0_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE1_ADDR 11
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE1_FIXPT 0x00003B40
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE1_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(15168)
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE1_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE2_ADDR 12
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE2_FIXPT 0x00004B00
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE2_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(19200)
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE2_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE3_ADDR 13
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE3_FIXPT 0x00004B60
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE3_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(19296)
|
||||
#define MOD_CHIMEWG1_ALG0_TIMINGTABLE3_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFGAINPOINTSINTABLE_ADDR 14
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFGAINPOINTSINTABLE_FIXPT 0x00000002
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFGAINPOINTSINTABLE_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(2)
|
||||
#define MOD_CHIMEWG1_ALG0_NUMBEROFGAINPOINTSINTABLE_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING0_ADDR 15
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING0_FIXPT 0x00000390
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING0_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(912)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING0_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING1_ADDR 16
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING1_FIXPT 0x00004B00
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING1_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(19200)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING1_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING2_ADDR 17
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING2_FIXPT 0x00004B60
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING2_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(19296)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINTIMING2_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES0_ADDR 18
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES0_FIXPT 0x00808CDC
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES0_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.00429871197835)
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES0_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES1_ADDR 19
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES1_FIXPT 0x0080003D
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.00000732045436)
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES2_ADDR 20
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES2_FIXPT 0x007FDF60
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES2_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.999004369228288)
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES2_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES3_ADDR 21
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES3_FIXPT 0x00800000
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES3_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_CHIMEWG1_ALG0_FREQUENCIES3_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGFREQ_ADDR 22
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGFREQ_FIXPT 0x00001B4E
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGFREQ_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.000833333333333333)
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGFREQ_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDFREQ_ADDR 23
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDFREQ_FIXPT 0x00001B4E
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDFREQ_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.000833333333333333)
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDFREQ_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS0_ADDR 24
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS0_FIXPT 0x0081A478
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS0_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1.01283168856871)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS0_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS1_ADDR 25
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS1_FIXPT 0x007FE70C
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(0.999238553400038)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS2_ADDR 26
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS2_FIXPT 0x00800000
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS2_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_CHIMEWG1_ALG0_GAINS2_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGGAIN_ADDR 27
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGGAIN_FIXPT 0x00000053
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGGAIN_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1E-05)
|
||||
#define MOD_CHIMEWG1_ALG0_STARTINGGAIN_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDGAIN_ADDR 28
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDGAIN_FIXPT 0x00000000
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDGAIN_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1E-07)
|
||||
#define MOD_CHIMEWG1_ALG0_LOWESTALLOWEDGAIN_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_CHIMEWG1_ALG0_MASK_ADDR 29
|
||||
#define MOD_CHIMEWG1_ALG0_MASK_FIXPT 0x000000FF
|
||||
#define MOD_CHIMEWG1_ALG0_MASK_VALUE SIGMASTUDIOTYPE_INTEGER_CONVERT(255)
|
||||
#define MOD_CHIMEWG1_ALG0_MASK_TYPE SIGMASTUDIOTYPE_INTEGER
|
||||
|
||||
/* Module S Splitter1 - Single Control Splitter*/
|
||||
#define MOD_SSPLITTER1_COUNT 1
|
||||
#define MOD_SSPLITTER1_DEVICE "IC1"
|
||||
#define MOD_SSPLITTER1_SINGLECTRLSPLIT1_ADDR 30
|
||||
#define MOD_SSPLITTER1_SINGLECTRLSPLIT1_FIXPT 0x00800000
|
||||
#define MOD_SSPLITTER1_SINGLECTRLSPLIT1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_SSPLITTER1_SINGLECTRLSPLIT1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Left Mixer - NxM Mixer*/
|
||||
#define MOD_LEFTMIXER_COUNT 3
|
||||
#define MOD_LEFTMIXER_DEVICE "IC1"
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_ADDR 31
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_FIXPT 0x00800000
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10000_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_ADDR 32
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_FIXPT 0x00800000
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10001_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10002_ADDR 33
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10002_FIXPT 0x00800000
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10002_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMIXER_ALG0_NXNMIXER1940ALG10002_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Right Mixer - NxM Mixer*/
|
||||
#define MOD_RIGHTMIXER_COUNT 3
|
||||
#define MOD_RIGHTMIXER_DEVICE "IC1"
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_ADDR 34
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20000_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_ADDR 35
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20001_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20002_ADDR 36
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20002_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20002_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMIXER_ALG0_NXNMIXER1940ALG20002_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Right Master - Single Volume*/
|
||||
#define MOD_RIGHTMASTER_COUNT 1
|
||||
#define MOD_RIGHTMASTER_DEVICE "IC1"
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_ADDR 37
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_FIXPT 0x00800000
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_RIGHTMASTER_GAIN1940ALGNS1_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
/* Module Left Master - Single Volume*/
|
||||
#define MOD_LEFTMASTER_COUNT 1
|
||||
#define MOD_LEFTMASTER_DEVICE "IC1"
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_ADDR 38
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_FIXPT 0x00800000
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_VALUE SIGMASTUDIOTYPE_FIXPOINT_CONVERT(1)
|
||||
#define MOD_LEFTMASTER_GAIN1940ALGNS2_TYPE SIGMASTUDIOTYPE_FIXPOINT
|
||||
|
||||
#endif
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC1_REG.h
|
||||
*
|
||||
* Created: Tuesday, April 26, 2022 9:47:52 AM
|
||||
* Created: Monday, May 2, 2022 9:54:40 AM
|
||||
* Description: H2201_V1:IC1 control register definitions.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
@@ -248,22 +248,22 @@
|
||||
/* CRC Ideal_1 - Registers (IC1) */
|
||||
#define REG_CRC_IDEAL_1_IC1_ADDR 0x40C0
|
||||
#define REG_CRC_IDEAL_1_IC1_BYTE 1
|
||||
#define REG_CRC_IDEAL_1_IC1_VALUE 0x7F
|
||||
#define REG_CRC_IDEAL_1_IC1_VALUE 0x37
|
||||
|
||||
/* CRC Ideal_2 - Registers (IC1) */
|
||||
#define REG_CRC_IDEAL_2_IC1_ADDR 0x40C1
|
||||
#define REG_CRC_IDEAL_2_IC1_BYTE 1
|
||||
#define REG_CRC_IDEAL_2_IC1_VALUE 0x7F
|
||||
#define REG_CRC_IDEAL_2_IC1_VALUE 0x43
|
||||
|
||||
/* CRC Ideal_3 - Registers (IC1) */
|
||||
#define REG_CRC_IDEAL_3_IC1_ADDR 0x40C2
|
||||
#define REG_CRC_IDEAL_3_IC1_BYTE 1
|
||||
#define REG_CRC_IDEAL_3_IC1_VALUE 0x60
|
||||
#define REG_CRC_IDEAL_3_IC1_VALUE 0x61
|
||||
|
||||
/* CRC Ideal_4 - Registers (IC1) */
|
||||
#define REG_CRC_IDEAL_4_IC1_ADDR 0x40C3
|
||||
#define REG_CRC_IDEAL_4_IC1_BYTE 1
|
||||
#define REG_CRC_IDEAL_4_IC1_VALUE 0x7F
|
||||
#define REG_CRC_IDEAL_4_IC1_VALUE 0x7C
|
||||
|
||||
/* CRC Enable - Registers (IC1) */
|
||||
#define REG_CRC_ENABLE_IC1_ADDR 0x40C4
|
||||
@@ -875,22 +875,22 @@
|
||||
#define R44_DEJITTER_IC1_SHIFT 0
|
||||
|
||||
/* CRC Ideal_1 (IC1) */
|
||||
#define R45_CRC_IDEAL_1_IC1 0x7F /* 01111111b [7:0] */
|
||||
#define R45_CRC_IDEAL_1_IC1 0x37 /* 00110111b [7:0] */
|
||||
#define R45_CRC_IDEAL_1_IC1_MASK 0xFF
|
||||
#define R45_CRC_IDEAL_1_IC1_SHIFT 0
|
||||
|
||||
/* CRC Ideal_2 (IC1) */
|
||||
#define R46_CRC_IDEAL_2_IC1 0x7F /* 01111111b [7:0] */
|
||||
#define R46_CRC_IDEAL_2_IC1 0x43 /* 01000011b [7:0] */
|
||||
#define R46_CRC_IDEAL_2_IC1_MASK 0xFF
|
||||
#define R46_CRC_IDEAL_2_IC1_SHIFT 0
|
||||
|
||||
/* CRC Ideal_3 (IC1) */
|
||||
#define R47_CRC_IDEAL_3_IC1 0x60 /* 01100000b [7:0] */
|
||||
#define R47_CRC_IDEAL_3_IC1 0x61 /* 01100001b [7:0] */
|
||||
#define R47_CRC_IDEAL_3_IC1_MASK 0xFF
|
||||
#define R47_CRC_IDEAL_3_IC1_SHIFT 0
|
||||
|
||||
/* CRC Ideal_4 (IC1) */
|
||||
#define R48_CRC_IDEAL_4_IC1 0x7F /* 01111111b [7:0] */
|
||||
#define R48_CRC_IDEAL_4_IC1 0x7C /* 01111100b [7:0] */
|
||||
#define R48_CRC_IDEAL_4_IC1_MASK 0xFF
|
||||
#define R48_CRC_IDEAL_4_IC1_SHIFT 0
|
||||
|
||||
@@ -1,603 +0,0 @@
|
||||
/*
|
||||
* File: C:\ESP_IDF_Projects\H2201_Audio_Mixer\ADAU1761\System\H2201_V1_IC1.h
|
||||
*
|
||||
* Created: Tuesday, April 26, 2022 9:47:52 AM
|
||||
* Description: H2201_V1:IC1 program data.
|
||||
*
|
||||
* This software is distributed in the hope that it will be useful,
|
||||
* but is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
|
||||
* CONDITIONS OF ANY KIND, without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
|
||||
*
|
||||
* This software may only be used to program products purchased from
|
||||
* Analog Devices for incorporation by you into audio products that
|
||||
* are intended for resale to audio product end users. This software
|
||||
* may not be distributed whole or in any part to third parties.
|
||||
*
|
||||
* Copyright ©2022 Analog Devices, Inc. All rights reserved.
|
||||
*/
|
||||
#ifndef __H2201_V1_IC1_H__
|
||||
#define __H2201_V1_IC1_H__
|
||||
|
||||
#include "SigmaStudioFW.h"
|
||||
#include "H2201_adau1761_reg.h"
|
||||
|
||||
#define DEVICE_ARCHITECTURE_IC1 "ADAU176x"
|
||||
#define DEVICE_ADDR_IC1 0x70
|
||||
|
||||
/* DSP Program Data */
|
||||
#define PROGRAM_SIZE_IC1 315
|
||||
#define PROGRAM_ADDR_IC1 2048
|
||||
ADI_REG_TYPE Program_Data_IC1[PROGRAM_SIZE_IC1] = {
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0xE0,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x34,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x2C,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x54,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x5C,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xF5,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x38,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0xE8,
|
||||
0x0C,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0x30,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xE8,
|
||||
0x07,
|
||||
0x20,
|
||||
0x08,
|
||||
0x00,
|
||||
0x00,
|
||||
0x06,
|
||||
0xA0,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xE0,
|
||||
0x00,
|
||||
0xC0,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x80,
|
||||
0x07,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0xC0,
|
||||
0x22,
|
||||
0x00,
|
||||
0x27,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0xE8,
|
||||
0x1E,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xE8,
|
||||
0x01,
|
||||
0x20,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xD8,
|
||||
0x01,
|
||||
0x03,
|
||||
0x00,
|
||||
0x00,
|
||||
0x07,
|
||||
0xC6,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0x08,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xF4,
|
||||
0x00,
|
||||
0x20,
|
||||
0x00,
|
||||
0xFF,
|
||||
0xD8,
|
||||
0x07,
|
||||
0x02,
|
||||
0x00,
|
||||
0xFD,
|
||||
0xA5,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0xFD,
|
||||
0xAD,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x08,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0xFD,
|
||||
0x25,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x10,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0xFD,
|
||||
0x2D,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x18,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x10,
|
||||
0x09,
|
||||
0x22,
|
||||
0x00,
|
||||
0x00,
|
||||
0x20,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x08,
|
||||
0x0A,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x18,
|
||||
0x0B,
|
||||
0x22,
|
||||
0x00,
|
||||
0x00,
|
||||
0x28,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x28,
|
||||
0x0C,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x30,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x20,
|
||||
0x0D,
|
||||
0x20,
|
||||
0x00,
|
||||
0x00,
|
||||
0x38,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x3D,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0xFD,
|
||||
0xB0,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x35,
|
||||
0x08,
|
||||
0x20,
|
||||
0x00,
|
||||
0xFD,
|
||||
0xB8,
|
||||
0x00,
|
||||
0xE2,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0x30,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0xFE,
|
||||
0xC0,
|
||||
0x0F,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
};
|
||||
|
||||
/* DSP Parameter (Coefficient) Data */
|
||||
#define PARAM_SIZE_IC1 56
|
||||
#define PARAM_ADDR_IC1 0
|
||||
ADI_REG_TYPE Param_Data_IC1[PARAM_SIZE_IC1] = {
|
||||
0x00,
|
||||
0x00,
|
||||
0x10,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x80,
|
||||
0x00,
|
||||
0x00,
|
||||
};
|
||||
|
||||
/* Register Default - IC1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R0_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x7F};
|
||||
|
||||
/* Register Default - IC1.DSP Run Register */
|
||||
ADI_REG_TYPE R1_DSP_RUN_REGISTER_IC1_Default[REG_DSP_RUN_REGISTER_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Clock Control Register */
|
||||
ADI_REG_TYPE R2_CLKCTRLREGISTER_IC1_Default[REG_CLKCTRLREGISTER_IC1_BYTE] = {
|
||||
0x0F};
|
||||
|
||||
/* Register Default - IC1.PLL Control Register */
|
||||
ADI_REG_TYPE R3_PLLCRLREGISTER_IC1_Default[REG_PLLCRLREGISTER_IC1_BYTE] = {
|
||||
0x00, 0x01, 0x00, 0x00, 0x20, 0x03};
|
||||
|
||||
/* Register Default - IC1.Delay */
|
||||
#define R4_DELAY_IC1_ADDR 0x0
|
||||
#define R4_DELAY_IC1_SIZE 2
|
||||
ADI_REG_TYPE R4_DELAY_IC1_Default[R4_DELAY_IC1_SIZE] = {
|
||||
0x00, 0x64};
|
||||
|
||||
/* Register Default - IC1.Serial Port Control Registers */
|
||||
#define R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_Default[R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.ALC Control Registers */
|
||||
#define R6_ALC_CONTROL_REGISTERS_IC1_SIZE 4
|
||||
ADI_REG_TYPE R6_ALC_CONTROL_REGISTERS_IC1_Default[R6_ALC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00, 0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.Microphone Control Register */
|
||||
ADI_REG_TYPE R7_MICCTRLREGISTER_IC1_Default[REG_MICCTRLREGISTER_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Record Input Signal Path Registers */
|
||||
#define R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE 8
|
||||
ADI_REG_TYPE R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_Default[R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x01, 0x05, 0x01, 0x05, 0x00, 0x00, 0x08};
|
||||
|
||||
/* Register Default - IC1.ADC Control Registers */
|
||||
#define R9_ADC_CONTROL_REGISTERS_IC1_SIZE 3
|
||||
ADI_REG_TYPE R9_ADC_CONTROL_REGISTERS_IC1_Default[R9_ADC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x13, 0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.Playback Output Signal Path Registers */
|
||||
#define R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE 14
|
||||
ADI_REG_TYPE R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_Default[R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE] = {
|
||||
0x61, 0x00, 0x61, 0x00, 0x0A, 0x0A, 0x00, 0xE7, 0xE7, 0x02, 0x02, 0xE7, 0x00, 0x03};
|
||||
|
||||
/* Register Default - IC1.Converter Control Registers */
|
||||
#define R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R11_CONVERTER_CONTROL_REGISTERS_IC1_Default[R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.DAC Control Registers */
|
||||
#define R12_DAC_CONTROL_REGISTERS_IC1_SIZE 3
|
||||
ADI_REG_TYPE R12_DAC_CONTROL_REGISTERS_IC1_Default[R12_DAC_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0x03, 0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.Serial Port Pad Control Registers */
|
||||
#define R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE 1
|
||||
ADI_REG_TYPE R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_Default[R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0xAA};
|
||||
|
||||
/* Register Default - IC1.Communication Port Pad Control Registers */
|
||||
#define R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_Default[R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE] = {
|
||||
0xAA, 0x00};
|
||||
|
||||
/* Register Default - IC1.Jack Detect Pad Control Register */
|
||||
ADI_REG_TYPE R15_JACKREGISTER_IC1_Default[REG_JACKREGISTER_IC1_BYTE] = {
|
||||
0x08};
|
||||
|
||||
/* Register Default - IC1.DSP ON Register */
|
||||
ADI_REG_TYPE R21_DSP_ENABLE_REGISTER_IC1_Default[REG_DSP_ENABLE_REGISTER_IC1_BYTE] = {
|
||||
0x01};
|
||||
|
||||
/* Register Default - IC1.CRC Registers */
|
||||
#define R22_CRC_REGISTERS_IC1_SIZE 5
|
||||
ADI_REG_TYPE R22_CRC_REGISTERS_IC1_Default[R22_CRC_REGISTERS_IC1_SIZE] = {
|
||||
0x7F, 0x7F, 0x60, 0x7F, 0x01};
|
||||
|
||||
/* Register Default - IC1.GPIO Registers */
|
||||
#define R23_GPIO_REGISTERS_IC1_SIZE 4
|
||||
ADI_REG_TYPE R23_GPIO_REGISTERS_IC1_Default[R23_GPIO_REGISTERS_IC1_SIZE] = {
|
||||
0x07, 0x07, 0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.Non Modulo Registers */
|
||||
#define R24_NON_MODULO_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R24_NON_MODULO_REGISTERS_IC1_Default[R24_NON_MODULO_REGISTERS_IC1_SIZE] = {
|
||||
0x10, 0x00};
|
||||
|
||||
/* Register Default - IC1.Watchdog Registers */
|
||||
#define R25_WATCHDOG_REGISTERS_IC1_SIZE 5
|
||||
ADI_REG_TYPE R25_WATCHDOG_REGISTERS_IC1_Default[R25_WATCHDOG_REGISTERS_IC1_SIZE] = {
|
||||
0x00, 0x02, 0x00, 0x00, 0x00};
|
||||
|
||||
/* Register Default - IC1.Sampling Rate Setting Register */
|
||||
ADI_REG_TYPE R26_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x7F};
|
||||
|
||||
/* Register Default - IC1.Routing Matrix Inputs Register */
|
||||
ADI_REG_TYPE R27_ROUTING_MATRIX_INPUTS_IC1_Default[REG_ROUTING_MATRIX_INPUTS_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Routing Matrix Outputs Register */
|
||||
ADI_REG_TYPE R28_ROUTING_MATRIX_OUTPUTS_IC1_Default[REG_ROUTING_MATRIX_OUTPUTS_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Serial Data Configuration Register */
|
||||
ADI_REG_TYPE R29_SERIAL_DATAGPIO_PIN_CONFIG_IC1_Default[REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.DSP Slew Mode Register */
|
||||
ADI_REG_TYPE R30_DSP_SLEW_MODES_IC1_Default[REG_DSP_SLEW_MODES_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Serial Port Sample Rate Register */
|
||||
ADI_REG_TYPE R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_Default[REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Clock Enable Registers */
|
||||
#define R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE 2
|
||||
ADI_REG_TYPE R32_CLOCK_ENABLE_REGISTERS_IC1_Default[R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE] = {
|
||||
0x7F, 0x03};
|
||||
|
||||
/* Register Default - IC1.Sample Rate Setting */
|
||||
ADI_REG_TYPE R35_SAMPLE_RATE_SETTING_IC1_Default[REG_SAMPLE_RATE_SETTING_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.DSP Run Register */
|
||||
ADI_REG_TYPE R36_DSP_RUN_REGISTER_IC1_Default[REG_DSP_RUN_REGISTER_IC1_BYTE] = {
|
||||
0x01};
|
||||
|
||||
/* Register Default - IC1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R37_DEJITTER_REGISTER_CONTROL_IC1_Default[REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE] = {
|
||||
0x00};
|
||||
|
||||
/* Register Default - IC1.Dejitter Register Control */
|
||||
ADI_REG_TYPE R38_DEJITTER_REGISTER_CONTROL_IC1_Default[REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE] = {
|
||||
0x03};
|
||||
|
||||
/*
|
||||
* Default Download
|
||||
*/
|
||||
#define DEFAULT_DOWNLOAD_SIZE_IC1 39
|
||||
|
||||
void default_download_IC1()
|
||||
{
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R0_SAMPLE_RATE_SETTING_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DSP_RUN_REGISTER_IC1_ADDR, REG_DSP_RUN_REGISTER_IC1_BYTE, R1_DSP_RUN_REGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_CLKCTRLREGISTER_IC1_ADDR, REG_CLKCTRLREGISTER_IC1_BYTE, R2_CLKCTRLREGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_PLLCRLREGISTER_IC1_ADDR, REG_PLLCRLREGISTER_IC1_BYTE, R3_PLLCRLREGISTER_IC1_Default);
|
||||
SIGMA_WRITE_DELAY(DEVICE_ADDR_IC1, R4_DELAY_IC1_SIZE, R4_DELAY_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SERIAL_PORT_CONTROL_0_IC1_ADDR, R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_SIZE, R5_SERIAL_PORT_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_ALC_CONTROL_0_IC1_ADDR, R6_ALC_CONTROL_REGISTERS_IC1_SIZE, R6_ALC_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_MICCTRLREGISTER_IC1_ADDR, REG_MICCTRLREGISTER_IC1_BYTE, R7_MICCTRLREGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_RECORD_PWR_MANAGEMENT_IC1_ADDR, R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE, R8_RECORD_INPUT_SIGNAL_PATH_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_ADC_CONTROL_0_IC1_ADDR, R9_ADC_CONTROL_REGISTERS_IC1_SIZE, R9_ADC_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_PLAYBACK_MIXER_LEFT_CONTROL_0_IC1_ADDR, R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_SIZE, R10_PLAYBACK_OUTPUT_SIGNAL_PATH_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_CONVERTER_CTRL_0_IC1_ADDR, R11_CONVERTER_CONTROL_REGISTERS_IC1_SIZE, R11_CONVERTER_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DAC_CONTROL_0_IC1_ADDR, R12_DAC_CONTROL_REGISTERS_IC1_SIZE, R12_DAC_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SERIAL_PORT_PAD_CONTROL_0_IC1_ADDR, R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE, R13_SERIAL_PORT_PAD_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_COMM_PORT_PAD_CTRL_0_IC1_ADDR, R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_SIZE, R14_COMMUNICATION_PORT_PAD_CONTROL_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_JACKREGISTER_IC1_ADDR, REG_JACKREGISTER_IC1_BYTE, R15_JACKREGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DSP_ENABLE_REGISTER_IC1_ADDR, REG_DSP_ENABLE_REGISTER_IC1_BYTE, R21_DSP_ENABLE_REGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_CRC_IDEAL_1_IC1_ADDR, R22_CRC_REGISTERS_IC1_SIZE, R22_CRC_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_GPIO_0_CONTROL_IC1_ADDR, R23_GPIO_REGISTERS_IC1_SIZE, R23_GPIO_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_NON_MODULO_RAM_1_IC1_ADDR, R24_NON_MODULO_REGISTERS_IC1_SIZE, R24_NON_MODULO_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_WATCHDOG_ENABLE_IC1_ADDR, R25_WATCHDOG_REGISTERS_IC1_SIZE, R25_WATCHDOG_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R26_SAMPLE_RATE_SETTING_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_ROUTING_MATRIX_INPUTS_IC1_ADDR, REG_ROUTING_MATRIX_INPUTS_IC1_BYTE, R27_ROUTING_MATRIX_INPUTS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_ROUTING_MATRIX_OUTPUTS_IC1_ADDR, REG_ROUTING_MATRIX_OUTPUTS_IC1_BYTE, R28_ROUTING_MATRIX_OUTPUTS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_ADDR, REG_SERIAL_DATAGPIO_PIN_CONFIG_IC1_BYTE, R29_SERIAL_DATAGPIO_PIN_CONFIG_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DSP_SLEW_MODES_IC1_ADDR, REG_DSP_SLEW_MODES_IC1_BYTE, R30_DSP_SLEW_MODES_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_BYTE, R31_SERIAL_PORT_SAMPLE_RATE_SETTING_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_CLOCK_ENABLE_REG_0_IC1_ADDR, R32_CLOCK_ENABLE_REGISTERS_IC1_SIZE, R32_CLOCK_ENABLE_REGISTERS_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PROGRAM_ADDR_IC1, PROGRAM_SIZE_IC1, Program_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, PARAM_ADDR_IC1, PARAM_SIZE_IC1, Param_Data_IC1);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_SAMPLE_RATE_SETTING_IC1_ADDR, REG_SAMPLE_RATE_SETTING_IC1_BYTE, R35_SAMPLE_RATE_SETTING_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DSP_RUN_REGISTER_IC1_ADDR, REG_DSP_RUN_REGISTER_IC1_BYTE, R36_DSP_RUN_REGISTER_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DEJITTER_REGISTER_CONTROL_IC1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE, R37_DEJITTER_REGISTER_CONTROL_IC1_Default);
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, REG_DEJITTER_REGISTER_CONTROL_IC1_ADDR, REG_DEJITTER_REGISTER_CONTROL_IC1_BYTE, R38_DEJITTER_REGISTER_CONTROL_IC1_Default);
|
||||
}
|
||||
|
||||
#endif
|
||||
69
ESP32/main/H2201_buttons.c
Normal file
69
ESP32/main/H2201_buttons.c
Normal file
@@ -0,0 +1,69 @@
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <stdlib.h>
|
||||
#include "freertos/FreeRTOS.h"
|
||||
#include "freertos/task.h"
|
||||
#include "freertos/queue.h"
|
||||
#include "driver/gpio.h"
|
||||
#include "driver/adc.h"
|
||||
|
||||
#include "H2201_buttons.h"
|
||||
#include "H2201_i2c.h"
|
||||
|
||||
static QueueHandle_t H2201_button_event_queue = NULL;
|
||||
|
||||
static void IRAM_ATTR gpio_isr_handler(void *arg)
|
||||
{
|
||||
uint32_t gpio_num = (uint32_t)arg;
|
||||
xQueueSendFromISR(H2201_button_event_queue, &gpio_num, NULL);
|
||||
}
|
||||
|
||||
static void H2201_button_task(void *arg)
|
||||
{
|
||||
uint32_t io_num;
|
||||
for (;;)
|
||||
{
|
||||
if (xQueueReceive(H2201_button_event_queue, &io_num, portMAX_DELAY))
|
||||
{
|
||||
int level = gpio_get_level(io_num);
|
||||
printf("GPIO[%d] intr, val: %d\n", io_num, level);
|
||||
if (level == 0)
|
||||
{
|
||||
H2201_i2c_beep();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void H2201_buttons_init(void)
|
||||
{
|
||||
gpio_config_t io_conf = {};
|
||||
|
||||
// interrupt of rising edge
|
||||
io_conf.intr_type = GPIO_INTR_ANYEDGE;
|
||||
io_conf.pin_bit_mask = ((1ULL << BUTTON_1) | (1ULL << BUTTON_2) | (1ULL << BUTTON_3) | (1ULL << BUTTON_4));
|
||||
|
||||
io_conf.mode = GPIO_MODE_INPUT;
|
||||
gpio_config(&io_conf);
|
||||
|
||||
// Please do not use the interrupt of GPIO36 and GPIO39 when using ADC or Wi-Fi with sleep mode enabled.
|
||||
// Please refer to the comments of `adc1_get_raw`.
|
||||
// Please refer to section 3.11 of 'ECO_and_Workarounds_for_Bugs_in_ESP32' for the description of this issue.
|
||||
// As a workaround, call adc_power_acquire() in the app. This will result in higher power consumption (by ~1mA),
|
||||
// but will remove the glitches on GPIO36 and GPIO39.
|
||||
adc_power_acquire();
|
||||
|
||||
H2201_button_event_queue = xQueueCreate(10, sizeof(uint32_t));
|
||||
xTaskCreate(H2201_button_task, "H2201_button_task", 2048, NULL, 10, NULL);
|
||||
|
||||
// install gpio isr service
|
||||
gpio_install_isr_service(ESP_INTR_FLAG_EDGE);
|
||||
// hook isr handler for specific gpio pin
|
||||
gpio_isr_handler_add(BUTTON_1, gpio_isr_handler, (void *)BUTTON_1);
|
||||
// hook isr handler for specific gpio pin
|
||||
gpio_isr_handler_add(BUTTON_2, gpio_isr_handler, (void *)BUTTON_2);
|
||||
// hook isr handler for specific gpio pin
|
||||
gpio_isr_handler_add(BUTTON_3, gpio_isr_handler, (void *)BUTTON_3);
|
||||
// hook isr handler for specific gpio pin
|
||||
gpio_isr_handler_add(BUTTON_4, gpio_isr_handler, (void *)BUTTON_4);
|
||||
}
|
||||
16
ESP32/main/H2201_buttons.h
Normal file
16
ESP32/main/H2201_buttons.h
Normal file
@@ -0,0 +1,16 @@
|
||||
#ifndef __H2201_BUTTONS_H__
|
||||
#define __H2201_BUTTONS_H__
|
||||
|
||||
|
||||
#define BUTTON_1 36
|
||||
#define BUTTON_2 39
|
||||
#define BUTTON_3 34
|
||||
#define BUTTON_4 35
|
||||
|
||||
/**
|
||||
* @brief setup button I/O
|
||||
*/
|
||||
void H2201_buttons_init(void);
|
||||
|
||||
|
||||
#endif /* __H2201_BUTTONS_H__*/
|
||||
@@ -3,7 +3,9 @@
|
||||
#include "driver/i2c.h"
|
||||
|
||||
#include "H2201_i2c.h"
|
||||
#include "H2201_adau1761.h"
|
||||
#include "H2201_V1_IC1.h"
|
||||
#include "H2201_V1_IC1_PARAM.h"
|
||||
#include "SigmaStudioFW.h"
|
||||
|
||||
void H2201_i2c_master_init(void)
|
||||
{
|
||||
@@ -32,163 +34,14 @@ void H2201_i2c_master_init(void)
|
||||
void H2201_i2c_adau1761_init(void)
|
||||
{
|
||||
default_download_IC1();
|
||||
|
||||
// i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
// i2c_master_start(cmd);
|
||||
|
||||
// i2c_master_write_byte(cmd, (OLED_I2C_ADDRESS << 1) | I2C_MASTER_WRITE, true);
|
||||
// i2c_master_write_byte(cmd, OLED_CONTROL_BYTE_CMD_STREAM, true);
|
||||
|
||||
// i2c_master_write_byte(cmd, OLED_CMD_SET_CHARGE_PUMP, true);
|
||||
// i2c_master_write_byte(cmd, 0x14, true);
|
||||
|
||||
// i2c_master_write_byte(cmd, OLED_CMD_SET_SEGMENT_REMAP, true); // reverse left-right mapping
|
||||
// i2c_master_write_byte(cmd, OLED_CMD_SET_COM_SCAN_MODE, true); // reverse up-bottom mapping
|
||||
|
||||
// i2c_master_write_byte(cmd, OLED_CMD_DISPLAY_ON, true);
|
||||
// i2c_master_stop(cmd);
|
||||
|
||||
// esp_err_t err = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 10 / portTICK_PERIOD_MS);
|
||||
// if (err == ESP_OK)
|
||||
// {
|
||||
// ESP_LOGI(H2201_I2C_TAG, "ADAU1761 configured successfully");
|
||||
// }
|
||||
// else
|
||||
// {
|
||||
// ESP_LOGE(H2201_I2C_TAG, "ADAU1761 configuration failed. code: 0x%.2X", err);
|
||||
// }
|
||||
|
||||
// i2c_cmd_link_delete(cmd);
|
||||
}
|
||||
|
||||
//-----------------------------------------
|
||||
// void select_register(uint8_t device_address, uint8_t register_address)
|
||||
// {
|
||||
// i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
// i2c_master_start(cmd);
|
||||
// i2c_master_write_byte(cmd, (device_address << 1) | I2C_MASTER_WRITE, 1);
|
||||
// i2c_master_write_byte(cmd, register_address, 1);
|
||||
// i2c_master_stop(cmd);
|
||||
// i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);
|
||||
// i2c_cmd_link_delete(cmd);
|
||||
// }
|
||||
|
||||
// int8_t esp32_i2c_read_bytes(uint8_t device_address, uint8_t register_address, uint8_t size, uint8_t *data)
|
||||
// {
|
||||
// select_register(device_address, register_address);
|
||||
// i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
// i2c_master_start(cmd);
|
||||
// i2c_master_write_byte(cmd, (device_address << 1) | I2C_MASTER_READ, 1);
|
||||
|
||||
// if (size > 1)
|
||||
// i2c_master_read(cmd, data, size - 1, 0);
|
||||
|
||||
// i2c_master_read_byte(cmd, data + size - 1, 1);
|
||||
|
||||
// i2c_master_stop(cmd);
|
||||
// i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);
|
||||
// i2c_cmd_link_delete(cmd);
|
||||
|
||||
// return (size);
|
||||
// }
|
||||
|
||||
// int8_t esp32_i2c_read_byte(uint8_t device_address, uint8_t register_address, uint8_t *data)
|
||||
// {
|
||||
// return (esp32_i2c_read_bytes(device_address, register_address, 1, data));
|
||||
// }
|
||||
|
||||
// int8_t esp32_i2c_read_bits(uint8_t device_address, uint8_t register_address, uint8_t bit_start, uint8_t size, uint8_t *data)
|
||||
// {
|
||||
// uint8_t bit;
|
||||
// uint8_t count;
|
||||
|
||||
// if ((count = esp32_i2c_read_byte(device_address, register_address, &bit)))
|
||||
// {
|
||||
// uint8_t mask = ((1 << size) - 1) << (bit_start - size + 1);
|
||||
|
||||
// bit &= mask;
|
||||
// bit >>= (bit_start - size + 1);
|
||||
// *data = bit;
|
||||
// }
|
||||
|
||||
// return (count);
|
||||
// }
|
||||
|
||||
// int8_t esp32_i2c_read_bit(uint8_t device_address, uint8_t register_address, uint8_t bit_number, uint8_t *data)
|
||||
// {
|
||||
// uint8_t bit;
|
||||
// uint8_t count = esp32_i2c_read_byte(device_address, register_address, &bit);
|
||||
|
||||
// *data = bit & (1 << bit_number);
|
||||
|
||||
// return (count);
|
||||
// }
|
||||
|
||||
// bool esp32_i2c_write_bytes(uint8_t device_address, uint8_t register_address, uint8_t size, uint8_t *data)
|
||||
// {
|
||||
// i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
// i2c_master_start(cmd);
|
||||
// i2c_master_write_byte(cmd, (device_address << 1) | I2C_MASTER_WRITE, 1);
|
||||
// i2c_master_write_byte(cmd, register_address, 1);
|
||||
// i2c_master_write(cmd, data, size - 1, 0);
|
||||
// i2c_master_write_byte(cmd, data[size - 1], 1);
|
||||
// i2c_master_stop(cmd);
|
||||
// i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);
|
||||
// i2c_cmd_link_delete(cmd);
|
||||
|
||||
// return (true);
|
||||
// }
|
||||
|
||||
// bool esp32_i2c_write_byte(uint8_t device_address, uint8_t register_address, uint8_t data)
|
||||
// {
|
||||
// i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
// i2c_master_start(cmd);
|
||||
// i2c_master_write_byte(cmd, (device_address << 1) | I2C_MASTER_WRITE, 1);
|
||||
// i2c_master_write_byte(cmd, register_address, 1);
|
||||
// i2c_master_write_byte(cmd, data, 1);
|
||||
// i2c_master_stop(cmd);
|
||||
// i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 1000 / portTICK_PERIOD_MS);
|
||||
// i2c_cmd_link_delete(cmd);
|
||||
|
||||
// return (true);
|
||||
// }
|
||||
|
||||
// bool esp32_i2c_write_bits(uint8_t device_address, uint8_t register_address, uint8_t bit_start, uint8_t size, uint8_t data)
|
||||
// {
|
||||
// uint8_t bit = 0;
|
||||
|
||||
// if (esp32_i2c_read_byte(device_address, register_address, &bit) != 0)
|
||||
// {
|
||||
// uint8_t mask = ((1 << size) - 1) << (bit_start - size + 1);
|
||||
// data <<= (bit_start - size + 1);
|
||||
// data &= mask;
|
||||
// bit &= ~(mask);
|
||||
// bit |= data;
|
||||
// return (esp32_i2c_write_byte(device_address, register_address, bit));
|
||||
// }
|
||||
// else
|
||||
// return (false);
|
||||
// }
|
||||
|
||||
bool esp32_i2c_write_bit(uint8_t device_address, uint8_t register_address, uint8_t bit_number, uint8_t data)
|
||||
void H2201_i2c_beep(void)
|
||||
{
|
||||
uint8_t bit;
|
||||
|
||||
esp32_i2c_read_byte(device_address, register_address, &bit);
|
||||
|
||||
if (data != 0)
|
||||
bit = (bit | (1 << bit_number));
|
||||
else
|
||||
bit = (bit & ~(1 << bit_number));
|
||||
|
||||
return (esp32_i2c_write_byte(device_address, register_address, bit));
|
||||
ADI_REG_TYPE beep_on[4] = {0x00, 0x80, 0x00, 0x00};
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, MOD_SWITCH1_ISON_ADDR, 4, beep_on);
|
||||
vTaskDelay(400 / portTICK_RATE_MS);
|
||||
ADI_REG_TYPE beep_off[4] = {0x00, 0x00, 0x00, 0x00};
|
||||
SIGMA_WRITE_REGISTER_BLOCK(DEVICE_ADDR_IC1, MOD_SWITCH1_ISON_ADDR, 4, beep_off);
|
||||
}
|
||||
|
||||
int8_t esp32_i2c_write_word(uint8_t device_address, uint8_t register_address, uint8_t data)
|
||||
{
|
||||
uint8_t data_1[] = {(uint8_t)(data >> 8), (uint8_t)(data & 0xFF)};
|
||||
|
||||
esp32_i2c_write_bytes(device_address, register_address, 2, data_1);
|
||||
|
||||
return (1);
|
||||
}
|
||||
|
||||
@@ -16,4 +16,6 @@
|
||||
void H2201_i2c_master_init(void);
|
||||
void H2201_i2c_adau1761_init(void);
|
||||
|
||||
void H2201_i2c_beep(void);
|
||||
|
||||
#endif /* __H2201_I2C_H__ */
|
||||
@@ -22,6 +22,9 @@
|
||||
|
||||
#include <stdint.h>
|
||||
#include <inttypes.h>
|
||||
#include "esp_log.h"
|
||||
#include "driver/i2c.h"
|
||||
#include "H2201_i2c.h"
|
||||
|
||||
/*
|
||||
* TODO: Update for your system's data type
|
||||
@@ -30,6 +33,7 @@ typedef unsigned short ADI_DATA_U16;
|
||||
typedef unsigned char ADI_REG_TYPE;
|
||||
|
||||
#define Address_Length 2
|
||||
void SIGMA_WRITE_REGISTER(uint8_t devAddress, uint16_t address, ADI_REG_TYPE data);
|
||||
void SIGMA_WRITE_REGISTER_BLOCK(uint8_t devAddress, uint16_t address, int length, ADI_REG_TYPE *pData);
|
||||
void SIGMA_WRITE_DELAY(int devAddress, int length, ADI_REG_TYPE *pData);
|
||||
|
||||
@@ -42,12 +46,32 @@ void SIGMA_WRITE_DELAY(int devAddress, int length, ADI_REG_TYPE *pData);
|
||||
/*
|
||||
* Write to a single Device register
|
||||
*/
|
||||
#define SIGMA_WRITE_REGISTER(devAddress, address, dataLength, data) \
|
||||
{ /*TODO: implement macro or define as function*/ \
|
||||
void SIGMA_WRITE_REGISTER(uint8_t devAddress, uint16_t address, ADI_REG_TYPE data)
|
||||
{
|
||||
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
||||
i2c_master_start(cmd);
|
||||
i2c_master_write_byte(cmd, devAddress, true); // write address 0x70
|
||||
i2c_master_write_byte(cmd, (address >> 8), true);
|
||||
i2c_master_write_byte(cmd, (address & 0xFF), true);
|
||||
|
||||
i2c_master_write_byte(cmd, data, true);
|
||||
// i2c_master_write(cmd, pData, length, true);
|
||||
|
||||
i2c_master_stop(cmd);
|
||||
esp_err_t err = i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 10 / portTICK_PERIOD_MS);
|
||||
if (err == ESP_OK)
|
||||
{
|
||||
ESP_LOGI(H2201_I2C_TAG, "ADAU1761 block write successfully");
|
||||
}
|
||||
else
|
||||
{
|
||||
ESP_LOGE(H2201_I2C_TAG, "ADAU1761 block write failed. code: 0x%.2X", err);
|
||||
}
|
||||
|
||||
i2c_cmd_link_delete(cmd);
|
||||
}
|
||||
|
||||
/*
|
||||
* TODO: CUSTOM MACRO IMPLEMENTATION
|
||||
* Write to multiple Device registers
|
||||
*/
|
||||
void SIGMA_WRITE_REGISTER_BLOCK(uint8_t devAddress, uint16_t address, int length, ADI_REG_TYPE *pData)
|
||||
@@ -78,7 +102,7 @@ void SIGMA_WRITE_REGISTER_BLOCK(uint8_t devAddress, uint16_t address, int length
|
||||
void SIGMA_WRITE_DELAY(int devAddress, int length, ADI_REG_TYPE *pData)
|
||||
{
|
||||
// int cnt=0;
|
||||
int nCount = 0;
|
||||
// int nCount = 0;
|
||||
// int data_length = length - Address_Length;
|
||||
// ADI_REG_TYPE data[4]={0x05, 0xF5, 0xE1, 0x00};
|
||||
// for(cnt=0; cnt<data_length; cnt++)
|
||||
@@ -94,9 +118,9 @@ void SIGMA_WRITE_DELAY(int devAddress, int length, ADI_REG_TYPE *pData)
|
||||
// nCount=0xFFFFFF;
|
||||
// nCount=0x15752A00; //5 secs approx
|
||||
// nCount=0x05F5E100; //5 secs approx
|
||||
nCount = 0xFFFFF;
|
||||
for (; nCount != 0; nCount--)
|
||||
;
|
||||
// nCount = 0xFFFFF;
|
||||
// for (; nCount != 0; nCount--)
|
||||
// ;
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -36,6 +36,7 @@
|
||||
#include "H2201_app.h"
|
||||
#include "H2201_avrcp.h"
|
||||
#include "H2201_a2dp.h"
|
||||
#include "H2201_buttons.h"
|
||||
|
||||
#define H2201_MAIN_TAG "H2201_MAIN"
|
||||
|
||||
@@ -61,6 +62,8 @@ void app_main(void)
|
||||
}
|
||||
ESP_ERROR_CHECK(err);
|
||||
|
||||
//H2201_buttons_init();
|
||||
|
||||
H2201_i2c_master_init();
|
||||
H2201_i2c_adau1761_init();
|
||||
|
||||
@@ -139,6 +142,8 @@ void app_main(void)
|
||||
// pin_code[2] = '3';
|
||||
// pin_code[3] = '4';
|
||||
// esp_bt_gap_set_pin(pin_type, 4, pin_code);
|
||||
|
||||
H2201_buttons_init();
|
||||
}
|
||||
|
||||
void h2201_gap_register_callback(esp_bt_gap_cb_event_t event, esp_bt_gap_cb_param_t *param)
|
||||
|
||||
Reference in New Issue
Block a user